掲載種別：研究論文（国際会議プロシーディングス）  

Test point insertion is an effective approach for improving fault diagnosis ability as well as testability. This paper presents a test points, as observation points, insertion for improving fault diagnosis ability. In order to find suitable observation points, scores are calculated on signal lines for each fault pair that is not distinguished by the given test set. After selecting observation points, the proposed method partitions primary outputs and the inserted observation points into groups such that the output responses in the same group are compacted by XOR operation. The partition method allows to reduce the number of values to be observed without decreasing the diagnosis ability. The effectiveness of the proposed method is validated by experiments on benchmark circuits.

DOI： 10.1109/ITC-CSCC58803.2023.10212844

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担当区分：責任著者   掲載種別：研究論文（国際会議プロシーディングス）  

Identifying optimal test points to maximize fault coverage is crucial for improving field tests of large-scale integrated circuits (LSIs). In this paper, we introduce Deep-TPs-Explorer, a method that utilizes deep graph-convolutional neural networks (GCNs) to identify a more effective set of test points, thereby enhancing the random testability of logic circuits. For efficient training of the GCN, we employ the Advantage Actor-Critic (A2C) reinforcement learning algorithm. The effectiveness of our proposed method is validated using the ISCAS89 and ITC99 benchmark circuits.

DOI： 10.1109/ITC-CSCC58803.2023.10212888

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

DOI： 10.11486/ejisso.37.0_13a1-2

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その他リンク： https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-22K11955/

担当区分：最終著者   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/DFT59622.2023.10313532

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その他リンク： https://dblp.uni-trier.de/db/conf/dft/dft2023.html#WangWMKHTSWN23

掲載種別：研究論文（国際会議プロシーディングス）  

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その他リンク： https://dblp.uni-trier.de/rec/conf/apnoms/2023

担当区分：責任著者   掲載種別：研究論文（学術雑誌）  

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その他リンク： https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-22K11955/

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者,　責任著者   掲載種別：研究論文（学術雑誌）   出版者・発行元：Association for Computing Machinery (ACM)  

Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST). Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method.

DOI： 10.1145/3563552

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/itc-cscc55581.2022.9894966

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記述言語：日本語   出版者・発行元：松山 : 愛媛大学大学教育総合センター  

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担当区分：筆頭著者   記述言語：日本語   出版者・発行元：国立研究開発法人 科学技術振興機構  

※本記事に抄録はありません。

DOI： 10.1241/sangakukanjournal.18.3_20

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掲載種別：研究論文（学術雑誌）  

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その他リンク： https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-22K11955/

担当区分：責任著者   記述言語：日本語   掲載種別：研究論文（学術雑誌）   出版者・発行元：一般社団法人エレクトロニクス実装学会  

DOI： 10.5104/jiep.24.668

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掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Use of a fault dictionary is an effective and efficient method for deducing candidate faults during fault diagnosis process. It contains output responses for every test pattern and every target fault, and therefore the size of the fault dictionary for large LSIs tends to be very large. This paper proposes methods for compacting a fault dictionary without loss of diagnosis ability. We assume that output responses are compacted by an XOR tree compactor, and we investigate how we make the groups of primary outputs for which values are compacted by XOR operation. The methods introduce measures that are based on the number of distinguished fault pairs and the number of detecting test patterns. The effectiveness of the proposed methods is demonstrated by conducting experiments on a number of benchmark circuits.

DOI： 10.1109/itc-cscc52171.2021.9501474

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

MRLD (TM) is a new type of reconfigurable device constructed by general SRAM array (multiple-LUTs) which has the advantages including small delay, low power and low production cost. It is therefore a promising alternative device for Artificial Intelligence applications such as neural networks (NNs). However, implementing a traditional NNs with fully connected NNs is a hard task due to the special interconnection structure of SRAM array (the multiple look-up tables: MLUTs) in MRLD. In this paper, we suggest a LUT-based neuron model to realize neuron functions by writing truth table in SRAM array, and propose a novel neural network structure named MNN (MRLD-based Neural Network) to adapt the special connection structure of MLUTs for implementing a NNs application into MRLD. To evaluate the effectiveness of MNN, we perform the experiments by training MNN with the MNIST dataset. The experimental results show that the MNN can get almost the same accuracy and loss for MNIST data recognition compared to a fully connected NN.

DOI： 10.1109/itc-cscc52171.2021.9501454

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electronics, Information and Communications Engineers (IEICE)  

DOI： 10.1587/transinf.2019edp7235

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担当区分：責任著者   記述言語：英語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

次世代のIoTエッジデバイス向けのメモリベース論理再構成デバイスMRLD(Memory-based Reconfigurable Logic Device）では，IoTシステムとしての高信頼性を保証するために，運用中に劣化状態を早期に検知・報告する劣化障害予告技術が求められる．本研究では，MRLDデバイスの構成要素であるLUTでの経年劣化による遅延を計測するために，MRLDデバイスの構造に適した遅延計測論理回路用リングオシレータを設計し，その実装方法を提案する。さらに，論理シュミレーションによって提案法の有効性を評価する。

DOI： 10.11486/ejisso.34.0_4c1-02

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

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記述言語：日本語   掲載種別：研究論文（大学，研究機関等紀要）   出版者・発行元：愛媛大学教育・学生支援機構  

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その他リンク： http://id.ndl.go.jp/bib/030370602

記述言語：日本語  

近年の組込みシステムの開発現場では，社会人が学生時代に学ばなかった新しい情報技術が用いられることがまれではなく，社会人の学びのニーズが高まっている．そこで，名古屋大学・静岡大学・広島大学・愛媛大学・南山大学の5大学は，社会人の組込みシステム技術者を育成するenPiT-Pro Embを提供して，社会のニーズに応えている．enPiT-Pro Embは，組込みシステムの中で車載とIoTに焦点を当てた教育を行っている．本稿では，特に車載組込みシステム技術者の育成に焦点を当てて，その取組み事例とそのプラクティスについて述べる．

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担当区分：責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

MRLD is a new type of reconfigurable device constructed by general SRAMs array that is promising to use for the next-generation IoT edge devices. During the operation of the MRLD, aging-induced failures may occur without any previous notice, which greatly affects the reliability of the entire IoT systems. In this paper, we propose a method for early detecting and reporting the effect of the aging in MRLD. The method configures a new designed ring oscillator circuit into the MRLD for monitoring its internal delay variations. Simulation results confirmed the effectiveness of the proposed method.

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掲載種別：研究論文（学術雑誌）  

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担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究論文（研究会，シンポジウム資料等）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ITC-CSCC.2019.8793429

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ITC-CSCC.2019.8793328

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担当区分：最終著者,　責任著者   記述言語：日本語   出版者・発行元：一般社団法人 電気学会  

DOI： 10.1541/ieejias.139.588

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その他リンク： http://id.ndl.go.jp/bib/029781066

担当区分：最終著者,　責任著者   記述言語：日本語  

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担当区分：最終著者   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/ATS47505.2019.000-4

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その他リンク： https://dblp.uni-trier.de/db/conf/ats/ats2019.html#HiramotoOT19

担当区分：最終著者,　責任著者   記述言語：日本語  

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担当区分：最終著者,　責任著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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担当区分：最終著者,　責任著者   記述言語：英語  

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE Computer Society  

Recently, reconfigurable devices are gaining increased attention for the development of IoT, Automotive and AI system. A new type of fine-grained reconfigurable device named MRLD (Memory Based Reconfigurable Logic Device) has been proposed which is constructed by general SRAMs without any programmable interconnect resources. It should be a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In this paper, we overview the architecture and the operation principle of MRLD. We also propose a test strategy and algorithms of pattern generation for the interconnect defects referred to stuck-at and bridge faults under MRLD. Experimental results confirmed the effectiveness of the proposed test method.

DOI： 10.1109/ATS.2017.16

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担当区分：最終著者,　責任著者   記述言語：日本語  

DOI： 10.5104/jiep.21.57

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担当区分：最終著者,　責任著者   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/MDAT.2018.2799801

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担当区分：最終著者   記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/ETS.2018.8400707

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その他リンク： https://dblp.uni-trier.de/db/conf/ets/ets2018.html#WangHTIMM18

担当区分：最終著者,　責任著者   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/ATS.2018.00038

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その他リンク： https://dblp.uni-trier.de/db/conf/ats/ats2018.html#WangAHTIMM18

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electronics, Information and Communication, Engineers, IEICE  

Small delay caused by a resistive open is difficult to test since circuit delay varies depending on various factors such as process variations and crosstalk even in fault-free circuits. We consider the problem of discriminating a resistive open by anomaly detection using delay distributions obtained by the effect of various input signals provided to adjacent lines. We examined the circuit delay in a fault-free circuit and a faulty circuit by applying electromagnetic simulator and circuit simulator for a line structure with adjacent lines under consideration of process variations. The effectiveness of the method that discriminates a resistive open is shown for the results obtained by the simulation.

DOI： 10.1587/transfun.E100.A.2842

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その他リンク： http://dblp.uni-trier.de/db/journals/ieicet/ieicet100a.html#journals/ieicet/YotsuyanagiIHHT17

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Institute of Electronics, Information and Communication, Engineers, IEICE  

In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.

DOI： 10.1587/transinf.2016EDL8210

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.

DOI： 10.1587/transinf.2016EDL8210

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その他リンク： http://dblp.uni-trier.de/db/journals/ieicet/ieicet100d.html#journals/ieicet/HigamiWTKS17

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掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE  

DOI： 10.1109/ISCIT.2017.8261186

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Information Processing Society of Japan  

For the purpose of analyzing the cause of delay in modern digital circuits, efficient diagnosis methods for delay faults need to be developed. This paper presents diagnosis methods for gate delay faults by using a fault dictionary approach. Although a fault dictionary is created by fault simulation and for a specific amount of delay, the proposed method using it can deduce candidate faults successfully even when the amount of delay in a circuit under diagnosis is different from that of the delay assumed during the fault simulation. In this paper, we target diagnosing the presence of single gate delay faults and double gate delay faults. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed methods.

DOI： 10.2197/ipsjtsldm.9.13

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その他リンク： http://dblp.uni-trier.de/db/journals/ipsj/ipsj9.html#journals/ipsj/HigamiWTKS16

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

BIST based field testing is a promising way to guarantee the functional safety of intelligent and autonomous systems. To improve the fault coverage with less random patterns for BIST, sequentially observing some flip-flops(FFs) during multi-cycle test is useful. In this paper, we propose the methodology for selecting the Fault-Detection-Strengthened FFs in multi-cycle test by evaluating the structure of a circuit. The experimental results of ITC99 benchmarks and a real Electronic Control Unit (ECU) circuit show the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction.

DOI： 10.1109/ATS.2016.40

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.2016.40

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：American Scientific Publishers  

High power dissipation in scan-based Logic-BIST testing is a vital issue. Low power approaches to handle all power problems of Logic-BIST have been proposed in our prior works, in which the toggle rate (switching activity) during the test operation (scan and capture) is well controlled. While significant reduction of the toggle rate has been confirmed, the amount of power reduction on a real chip is not known yet. In this paper, we implement the low power approaches on a Test Element Group (TEG) chip to investigate the physical effects of the low power scheme on a real chip in terms of current dissipation, voltage-drop and delay variations. Experimental results confirm the effectiveness of the low power scheme and show strong correlation between the simulated toggle rate and the measured (current, voltage-drop and delay variation) values. They show that the simulated toggle rate can be used as a good indicator of test power in test generation or design. The measured results of the actual power reduction caused by the toggle rate reduction should be valuable references to the low power test design.

DOI： 10.1166/jolpe.2015.1410

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記述言語：英語   掲載種別：論文集(書籍)内論文   出版者・発行元：Springer International Publishing  

Since the 3D integrated circuit (3D-IC) consists of several dies that are connected by the huge number of through-silicon vias (TSVs), the yield of a 3D-IC makes an impact on the chip cost. Therefore, development of testing technology for 3D-IC becomes essential for reducing the manufacturing cost of 3D-IC. In this chapter, we describe the testing technologies for 3D-IC. In Sect. 8.1, we marshal the issues that must be handled in the 3D-IC testing. From Sects. 8.2 to 8.4, we introduce the outlining of the proposed 3D-IC testing technologies in so far. From Sects. 8.5 to 8.7, we provide the 3D-IC testing technologies that are proposed by our research group in Japan.

DOI： 10.1007/978-3-319-18675-7_8

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

It is very difficult, if not impossible, to design hazard free circuits in view of substantial delay uncertainties of gates and interconnects implemented in submicron technologies. In this paper, we propose diagnosis methods for gate delay faults for such circuits. The fault simulation method employed by us uses eight values and calculates logic values as well as earliest transition times and latest transition times. It can deal with hazard signals more accurately than conventional methods. The proposed method uses a fault dictionary to deduce candidate faults which sufficiently explain the output responses of a circuit under diagnosis.

DOI： 10.1109/ISVLSI.2015.67

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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DOI： 10.11348/reajshinrai.36.8_501

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記述言語：日本語   出版者・発行元：日本信頼性学会  

微細化加工技術の進展に伴って,配線の物理的欠陥によって生じる多様な故障が問題となっている.多様な故障モデルを検出することを目的とした欠陥検出向けテストのために,これまでN回検出テスト集合を利用することが提案されている.しかしながら,設定された検出回数の増加に伴うテストパターン数の増加が問題である.本論文では,まず,故障励起関数に基づいて遷移故障テストパターンを評価する指針(欠陥検出確率)を提案する.次に,欠陥検出確率に基づいて,検出回数Nの値が大きなN回検出テスト集合からテストパターンを選択する手法を0-1整数計画問題として定式化する.評価実験結果から,提案法により得られたテスト集合は,テストパターン数の同じ遷移故障のN回検出テスト集合に比べて,より多様な故障モデルを検出できることを示す.

DOI： 10.11348/reajshinrai.36.8_501

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記述言語：日本語   掲載種別：研究論文（研究会，シンポジウム資料等）  

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記述言語：日本語   掲載種別：研究論文（研究会，シンポジウム資料等）  

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記述言語：日本語   出版者・発行元：日本信頼性学会  

鉄道の安全安定輸送に列車検知装置が果たす役割は極めて重要であり,軌道回路は列車検知装置の代表的な設備である.従来形と新しいタイプの軌道回路を比較し機器構成や各機器が持つ機能の再評価を通じて点検項目の見直しをおこなった.見直しの結果については点検項目を30%に絞込みかつ見直しをおこなった点検項目の安全性と信頼性の検証をFMEAとFTAを用いて行った.

DOI： 10.11348/reajshinrai.36.6_391

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：日本語   出版者・発行元：日本信頼性学会  

DOI： 10.11348/reajsym.2014spring.22.0_47

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記述言語：日本語   掲載種別：研究論文（学術雑誌）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper presents a diagnosis method for gate delay faults in the presence of clock delay faults. The method deduces candidate faults using a single gate delay fault dictionary and a single clock delay fault dictionary, which contain the information of latest transition time of signals as well as output logic values. To reduce the diagnostic ambiguity we remove those faults from the candidate fault list which provide a contradiction between the circuit responses and responses stored in the dictionary. Since the dictionary is not generated by considering the simultaneous existence of a gate delay fault and a clock delay fault, some heuristic parameters are introduced in order to compensate the difference between the dictionaries and the responses in a circuit under diagnosis.

DOI： 10.1109/ISVLSI.2014.60

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2014.60

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：The Japan Institute of Electronics Packaging  

In this paper, we introduce a method to measure the resistance of high density post-bond Through Silicon Via (TSV) including serial micro-bumps and bond resistance in Three Dimensional Stacked IC (3D-SIC). The key idea of our technology is to use Electrical Probes embedded in stacked silicon dies. It is a measuring circuit based on Analog Boundary-Scan (IEEE 1149.4). The standard Analog Boundary-Scan structure is modified to realize high measuring accuracy for TSVs in 3D-SIC. The main contribution of the method is to measure the resistance of high pin count (e.g. >10,000) post-bond TSVs accurately. Electrical Probes correspond to the high density of TSV (e.g. < 40 um pitch) and work like Kelvin probe. The measurement accuracy is less than 10 mΩ. We also introduce the preliminary results of small scale measuring experiments and the results of SPICE simulation of large scale measuring circuits.

DOI： 10.5104/jiepeng.7.140

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   出版者・発行元：EDIZIONI NUOVA CULTURA  

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その他リンク： http://dblp.uni-trier.de/db/journals/ieicet/ieicet96d.html#journals/ieicet/Takahashi13

記述言語：日本語   出版者・発行元：日本信頼性学会  

DOI： 10.11348/reajsym.2013autumn.26.0_67

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

電子機器の小型化・高機能化に伴って,実装ボード上のIC間の相互接続をテストするためのバウンダリスキャンテストが必要不可欠となりつつある.本論文では,これまでほとんど論じられることがなかった,バウンダリスキャンテスト実行中のIC内部で起こっている回路の振舞いを分析し,テスト上の課題について言及する.更に,その課題に対する対策を述べる.

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1587/transinf.E96.D.1323

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その他リンク： http://dblp.uni-trier.de/db/journals/ieicet/ieicet96d.html#journals/ieicet/HigamiTKS13

記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

半断線故障が発生すると,故障配線の信号遅延により回路性能が低下する場合がある しかし,故障配線に信号遷移を与える検査入力を印加しても論理回路動作が正常となる場合もあり,半断線故障の検出は困難である 本研究では,半断線故障の検出のために故障発生時の出力特性を電磁界シミュレーションを用いて調査した半断線故障発生時の出力信号へ影響を及ぼすと考えられる欠陥規模,隣接配線長およひ隣接配線への入力信号を考慮して,半断線故障を含む配線レイアウトを作成し,各要素が故障発生時の遅延時間に与える変化量を信号遅延解析結果より示す.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant of the faulty line but it is also dependent on the signal transition(s) on its adjacent lines. In this paper, we propose an efficient simulation method to simulate small delay faults and we use this simulator to diagnose resistive open faults. The fault simulator developed by us simulates all delay faults for one signal line simultaneously. This information is then used to deduce the candidate faulty lines in two steps. Experimental results for ISCAS'89 benchmark circuits show that by using the method proposed by us the faulty lines can be identified correctly in most cases.

DOI： 10.1109/ATS.2013.23

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.2013.23

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose a test generation method for diagnosing transition faults. The proposed method assumes launch on capture test, and it generates test vectors for given fault pairs using a stuck-at ATPG tool so that they can be distinguished. If a given fault pair is indistinguishable, it is identified, and thus the proposed method achieves a complete diagnostic test generation. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at fault, and some additional logic gates are inserted in a CUT during the test generation process. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguished by commercial tools, and also identify indistinguishable fault pairs.

DOI： 10.1587/transinf.E95.D.1093

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その他リンク： http://dblp.uni-trier.de/db/journals/ieicet/ieicet95d.html#journals/ieicet/HigamiOYTSA12

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE Computer Society  

This paper presents diagnosis methods for bridging faults between a clock line and a gate signal line. Scan-based simulation methods are applied while assuming that only scan-based flush tests are used. In view of the fact that initial states play an important role, we consider two possible scenarios: 1) all flip-flops are assumed to be reset table, and 2) flip-flops are not reset table. In order to handle unknown states due to the non-reset table flip-flops, we introduce heuristic techniques. The effectiveness of the proposed methods are evaluated by the experimental results for benchmark circuits. © 2012 IEEE.

DOI： 10.1109/PRDC.2012.15

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その他リンク： http://dblp.uni-trier.de/db/conf/prdc/prdc2012.html#conf/prdc/HigamiTKS12

記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

LSIの微細化技術の進展並びに高集積化・高速化に伴い,論理回路の故障診断は,(1)故障原因を調べてテストへフィードバックすることでLSIの品質を向上させること,(2)製造プロセスの歩留りを決めるプロセスの欠陥や設計の不具合を調べ,その対策を施すことで製造歩留りを向上させること,などの手段として近年その重要性を増している.そこで,本論文では,論理回路の故障診断法について概説する.まず,故障診断法の基本概念として,故障モデル及び故障診断法の基本的な方法である原因-結果分析法と結果-原因分析法を簡単に説明する.次に,複雑な故障に対応する故障診断技術の発展の観点から,論理回路の故障診断法を「論理故障ベース診断法」と「欠陥ベース診断法」に分類し,それらの概要を述べる.本論文では,単一縮退故障,多重縮退故障,ブリッジ故障,オープン故障及びX故障に対してこれまで開発されている論理故障ベース診断法をそれぞれ概説する.また,ブリッジ故障,オープン故障及びセル内故障に対してこれまで開発されている欠陥ベース診断法をそれぞれ概説する.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

In this paper, we investigate the effects of delay faults on clock lines under launch-on-capture test strategy. In this fault model we assume that scan-in and scan-out operations, being relatively slow, can perform correctly even in the presence of a fault. However, a flip-flop may fail to capture a value at correct timing during system clock operation, thus requiring the use of launch-on-capture test strategy to detect such a fault. In the paper, we first show simulation results providing a relation between the duration of the delay and difficulty of detecting such faults in the launch-on-capture test. Next, we propose test generation methods to detect such clock delay faults, and show some experimental results to establish the effectiveness of our methods.

DOI： 10.1109/ASPDAC.2011.5722299

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その他リンク： https://dblp.uni-trier.de/rec/conf/aspdac/2011

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Shrinking timing margins for modern high speed digital circuits require a careful reconsideration of faults and fault models. In this paper, we discuss detection of transition faults in the presence of small clock delay faults. We first show that in the presence of a delay fault on a clock line some transition faults may fail to be detected. We propose a test generation method for detecting such faults (simultaneous presence of two faults) which consist of a gate transition fault and a clock delay fault assuming launch-on-capture test environment. The proposed test generation method employs a standard stuck-at ATPG tool. In our test generation methodology, the conditions for detecting a clock delay fault are converted into those for detecting a stuck-at fault, by adding some modeling logic during the ATPG process. Experimental results for benchmark circuits show the effectiveness of the proposed methods.

DOI： 10.1109/ATS.2011.33

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.2011.33

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

With shrinking of LSIs, the diversification of defective mode becomes a critical issue. As a result, test patterns for stuck-at faults and transition faults are insufficient to detect such defects. N-detection tests have been known as an effective way for achieving high defect coverage, but the large number of test pattern counts is the problem. In this paper, we propose metrics based on the fault excitation functions and the propagation path function to evaluate test patterns for transition faults. We also propose the method for selecting the test patterns from the N-detection test set. From the experimental results, we show that the set of selected test patterns can detect the larger number of faults than other test set with the same number of test patterns.

DOI： 10.1109/ATS.2011.24

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.2011.24

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

This paper addresses the problem of simultaneous presence of multiple faults consisting of clock delay and gate transitions faults. The conditions of detecting a target multiple fault are converted into those for detecting a single stuck-at fault by adding some logic during the ATPG process. Experimental results show the effectiveness of our method by achieving nearly 100% fault efficiency.

DOI： 10.1109/ETS.2011.27

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ETS.2011.27

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記述言語：英語   掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/ISCIT.2010.5665061

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

Faulty effects caused by a hard open defect at an interconnect line in a 90nm CMOS IC are analyzed by device simulation in this paper. The simulation results reveal us that output voltage of the floating interconnect line is obtained as linear sum of effects from logic signals of the adjacent interconnect lines and the defective one. Also, an estimation model of voltage at the floating interconnect line is proposed. Feasibility of the estimation is examined in this paper. The result shows us that the voltage can be estimated within error of about 0.03V. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665062

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.

DOI： 10.1587/transfun.E92.A.3128

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その他リンク： http://dblp.uni-trier.de/db/journals/ieicet/ieicet92a.html#journals/ieicet/HigamiSTKT09

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Under the open fault model with considering the effects of adjacent lines, the open fault excitation is depended on the tests. Therefore, the layout information is needed to generate a test For an open fault. However, it is not easy to extract accurate circuit parameters of a deep sub-micron LSI. We have already proposed an open fault model without using the accurate circuit parameters [6]-[8]. In this paper, we propose a new class of the pair of tests For the open fault called Ordered Pair of Tests (OPT). OPT is generated based on the fault excitation function as a threshold function of the adjacent lines. Also we propose a method for generating OPTs from the given stuck-at fault test set. The proposed method generates OPTs using only information about adjacent lines of the target open fault. Experimental results show that the proposed method can generate the OPTs for the open faults with high fault coverage.

DOI： 10.1109/ATS.2009.39

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.2009.39

記述言語：英語   掲載種別：研究論文（学術雑誌）  

Conventional stuck-at fault model is no longer sufficient to deal with the problems of nanometer geometries in modern Large Scale Integrated Circuits (LSIs). Test and diagnosis for transistor defects are required. In this paper we propose a fault diagnosis method for transistor shorts in combinational and full-scan circuits that are described at gale level design. Since it is difficult to describe the precise behavior of faulty transistors, we define two types of transistor short models by focusing on the output values of the corresponding faulty gate. Some of the salient features of the proposed diagnosis method are 1) it uses only gate-level simulation and does not use transistor-level simulation like SPICE, 2) it uses conventional stuck-at fault simulator yet it is able to handle transistor shorts, thus suitable for large circuits, and 3) it is efficient and accurate. We apply our method to ISCAS benchmark circuits to demonstrate the effectiveness of our method. © 2009 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.2.250

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper presents a diagnostic test generation method for transition faults. As two consecutive vectors application mechanism, launch on capture test is considered. The proposed algorithm generates test vectors for given fault pairs using a stuck-at ATPG tool so that they are distinguished. If a given fault pair is indistinguishable, it is identified. Therefore the proposed algorithm provides a complete test generation regarding the distinguishability. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at fault, and some additional logic are inserted in a CUT for the test generation. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguished by commercial tools, and also identify all the indistinguishable fault pairs.

DOI： 10.1109/TEST.2009.5355681

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and vias often cause failure. Development of an efficient fault diagnosis method for open faults is desired. However, the diagnosis method for open faults has not been established yet. In this paper, we propose a novel approach for improving the diagnostic quality of open faults by introducing a threshold function in which the logical value of the line with open defect depends on the weighted logical values of its adjacent lines. By using the threshold function, we can deduce not only a faulty line but also an open defect site at the faulty line. Experimental results show that the proposed method can identify an exact faulty line in most cases with a very small computation cost. The proposed method can also identify the open defect site within 25%-length of the faulty line.

DOI： 10.1109/VLSI.Design.2009.53

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2009.53

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed in [10]. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared with the open fault model that calculate the weighted sum of voltages at the adjacent lines.

DOI： 10.1109/VLSI.Design.2009.60

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2009.60

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：Information and Media Technologies 編集運営会議  

Conventional stuck-at fault model is no longer sufficient to deal with the problems of nanometer geometries in modern Large Scale Integrated Circuits (LSIs). Test and diagnosis for transistor defects are required. In this paper we propose a fault diagnosis method for transistor shorts in combinational and full-scan circuits that are described at gale level design. Since it is difficult to describe the precise behavior of faulty transistors, we define two types of transistor short models by focusing on the output values of the corresponding faulty gate. Some of the salient features of the proposed diagnosis method are 1) it uses only gate-level simulation and does not use transistor-level simulation like SPICE, 2) it uses conventional stuck-at fault simulator yet it is able to handle transistor shorts, thus suitable for large circuits, and 3) it is efficient and accurate. We apply our method to ISCAS benchmark circuits to demonstrate the effectiveness of our method.

DOI： 10.11185/imt.4.727

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

Physical defects that are not covered by stuck-at fault or bridging fault model are increasing in LSI circuits designed and manufactured in modem Deep Sub-Micron (DSM) technologies. Therefore. it is necessary to target non-stuck-at and non-bridging faults. A stuck-open is one such fault model that captures transistor level defects. This paper presents two methods for maximizing stuck-open fault coverage using stuck-at test vectors. In this paper we assume that it test set to detect stuck-at faults is given and we consider two formulations for maximizing stuck-open coverage using the given test set as follows. The first problem is to form a test sequence by using each test vector multiple times, if needed, as long as the stuck-open coverage is increased. In this case the target is to make the resultant test sequence as short as possible under the constraint that the maximum stuck-open coverage is achieved using the given test set. The second problem is to form a test sequence by using each test vector exactly once only. Thus in this case the length of the test sequence is maintained as the number of given test vectors. In both formulations the stuck-at fault coverage does not change. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.

DOI： 10.1093/ietfec/e91-a.12.3506

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記述言語：日本語   掲載種別：研究論文（学術雑誌）  

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In general, we do not know which fault model can explain the cause of the faulty values at the primary outputs in a circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty value on the application of a failing test pattern. In this paper, we propose an effective diagnosis method on multiple fault models, based on only pass/fail information on the applied test patterns. The proposed method deduces both the fault model and the fault location based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing test patterns. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing test patterns. Experimental results show that our method can accurately identify the fault models (stuck-at fault model, AND/OR bridging fault model, dominance bridging fault model, or open fault model) for 90% faulty circuits and that the faulty sites are located within two candidate faults.

DOI： 10.1093/ietisy/e91-d.3.675

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper presents methods for detecting transistor short faults using logic level fault simulation and test generation. The paper considers two types of transistor level faults, namely strong shorts and weak shorts, which were introduced in our previous research. These faults are defined based on the values of outputs of faulty gates. The proposed fault simulation and test generation are performed using gate-level tools designed to deal with stuck-at faults, and no transistor-level tools are required. In the test generation process, a circuit is modified by inserting inverters, and a stuck-at test generator is used. The modification of a circuit does not mean a design-for-testability technique, as the modified circuit is used only during the test generation process. Further, generated test patterns are compacted by fault simulation. Also, since the weak short model involves uncertainty in its behavior, we define fault coverage and fault efficiency in three different way, namely, optimistic, pessimistic and probabilistic and assess them. Finally, experimental results for ISCAS benchmark circuits are used to demonstrate the effectiveness of the proposed methods.

DOI： 10.1093/ietisy/e91-d.3.690

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

With the increasing complexity of LSI, Built-In Self Test (BIST) is a promising technique for production testing. We herein propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We refer to fault diagnosis based on the ambiguous test pattern set obtained by the compressed responses of BIST as post-BIST fault diagnosis [1]. In the present paper, we propose an effective method by which to perform post-BIST fault diagnosis for multiple stuck-at faults. The efficiency of the success ratio and the feasibility of diagnosing large circuits are discussed.

DOI： 10.1093/ietisy/e91-d.3.771

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Defects in the modern LSIs manufactured by the deep-submicron technologies are known to cause complex faulty phenomena. Testing by targeting only stuck-at or bridging faults is no longer sufficient. Yet, increasing defect coverage is even more important. A stuck-open fault model considers transistor level defects, many of which are not covered by a stuck-at fault model. Further, test vectors for stuck-open faults also have the ability to detect the defects modeled by delay faults. This paper presents test generation methods for stuck-open, faults using stuck-at test vectors and stuck-at test generation tools. The resultant test vectors achieve high coverage of stuck open faults while maintaining the original stuck-at fault coverage, thus offering the benefit of potential better defect coverage. We consider two types of test application mechanisms, namely launch on capture test and enhanced scan test. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.

DOI： 10.1109/ATS.2008.39

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.2008.39

掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Springer  

DOI： 10.1007/978-3-540-85565-1_123

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その他リンク： https://dblp.uni-trier.de/db/conf/kes/kes2008-2.html#YamashitaTT08

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electronics, Information and Communication, Engineers, IEICE  

With the increasing complexity of LSI, Built-In Self Test (BIST) is a promising technique for production testing. We herein propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We refer to fault diagnosis based on the ambiguous test pattern set obtained by the compressed responses of BIST as post-BIST fault diagnosis [1]. In the present paper, we propose an effective method by which to perform post-BIST fault diagnosis for multiple stuck-at faults. The efficiency of the success ratio and the feasibility of diagnosing large circuits are discussed. Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.

DOI： 10.1093/ietisy/e91-d.3.771

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper proposes a theory of transistor short faults and their detection in logic test environment. We define transistor short models, and reveal the characteristics of equivalent faults and redundant faults. Also, we present a stuck-at fault simulation method and a test generation method that uses only the gate-level description of the circuits while dealing. with transistor short faults. We present experimental results for ISCAS benchmark circuits to demonstrate the effectiveness of the methodology proposed in this paper.

DOI： 10.1109/VLSID.2007.83

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.83

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

As semiconductor technologies progress, testing of small delay defects are becoming mode important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.

DOI： 10.1109/DFT.2007.30

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その他リンク： https://dblp.uni-trier.de/db/conf/dft/dft2007.html#AikyoTHOOT07

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Under the modem manufacturing technologies, the open defect is one of the significant issues to maintain the reliability of DSM circuits. However, the modeling and techniques for test and diagnosis for open faults have not been established yet. In this paper we give an important clue for modeling an open fault with considering the affects of adjacent lines. Firstly, we use computer simulations to analyze the defective behaviors of a line with the open defect. From the simulation results, we propose a new open fault model that is excited depending on the logic values at the adjacent lines assigned by a test. Next, we propose a diagnosis method that uses the pass/fail information to deduce the candidate open fault. Finally, experimental results show that the proposed method is able to diagnose the open faults with good resolution. It takes about 6 minutes to diagnose the open fault on the large circuit (2M gates).

DOI： 10.1109/ATS.2007.34

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その他リンク： https://dblp.uni-trier.de/db/conf/ats/ats2007.html#TakahashiHKATYT07

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

In order to ensure high quality of DSM circuits, testing for the open defect in the circuits is necessary. However, the modeling and techniques for test generation for open faults have not been established yet. In this paper, we propose a method for generating tests and diagnostic tests based on a new open fault model. Firstly, we show a new open fault model with considering adjacent lines [9]. Under the open fault model, we reveal more about the conditions to excite the open fault. Next we propose a method for generating tests for open faults by using a stuck-at fault test with don't cares. We also propose a method for generating a diagnostic test that can distinguish the pair of open faults. Finally, experimental results show that 1) the proposed method is able to achieve 100% fault coverages for almost all benchmark circuits and 2) the proposed method is able to reduce the number of indistinguished open fault pairs.

DOI： 10.1109/DFT.2007.11

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その他リンク： https://dblp.uni-trier.de/db/conf/dft/dft2007.html#TakahashiHKATYH07

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Test generation methods for transistor shorts using logic test environment are proposed. The fault models used are strong shorts and weak shorts, introduced in our earlier work. Our methodology consists of fault simulation, test generation and test compaction using gate-level tools to detect transistor faults but without resorting to use of transistor-level tools.

DOI： 10.1109/ATS.2007.64

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その他リンク： https://dblp.uni-trier.de/db/conf/ats/ats2007.html#HigamiSTKT07

記述言語：日本語   出版者・発行元：一般社団法人情報処理学会  

近年，論理回路のテストや故障診断におけるコスト削減が重要になってきている．テストや故障診断のコストは，印加されるテストベクトル数に依存するため，コスト削減のためにはテストベクトルを削減することが重要である．本論文では，組合せ回路および順序回路に対して，故障診断のためのテストベクトル数削減法（テスト圧縮法）を提案する．提案するテスト圧縮法では，与えられたテスト集合またはテスト系列に対して，区別される故障ペア数を減少させることなく，テストベクトル数を削減する．故障ペア数は故障数の2 乗に比例するため，大規模回路においてそれは膨大な数となる．そこで提案法では発見的手法を用いて，一度に取り扱う故障ペア数を減少させることによって，大規模回路においてもテストベクトル削減を可能にする．なお提案法では，検出・非検出情報に基づく故障診断を仮定する．これは，故障検出の有無だけの情報を用い，故障影響が観測される外部出力情報を用いない故障診断のことである．提案法の有効性は，ISCAS ベンチマーク回路に対する実験の結果によって示される．Recently, it is getting more important to reduce the cost of test and fault diagnosis. Since the cost of test and fault diagnosis depends on the number of test vectors, test vectors must be compacted. This paper presents methods for compacting of pass/fail-based diagnostic test sets or test sequences for combinational and sequential circuits. The pass/fail-based diagnosis uses only pass/fail information of test vectors but not information on location of primary outputs where faulty effects are observed. The proposed methods reduce the number of test vectors while maintaining the original diagnostic capability. In order to compact diagnostic test vectors, we must take care of a large number of fault pairs, which is the square number of faults. The proposed methods introduce heuristics to reduce the number of fault pairs that are handled at one time. The effectiveness of the proposed methods are shown by experimental results for ISCAS benchmark circuits.

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その他リンク： http://id.nii.ac.jp/1001/00010251/

記述言語：日本語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

DOI： 10.1109/ASPDAC.2006.1594761

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その他リンク： http://doi.acm.org/10.1145/1118299.1118455

記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

微細化技術の進展並びに高集積化・多層化に伴い,配線の接続不良によるオープン故障の診断が不可欠になっている.また,スキャンフリップフロップ数の増加及び組込み自己テスト(BIST)の導入によって,被検査回路の故障を検出するテストごとに誤りを観測する外部出力及びスキャンフリップフロップの位置を知ることが困難になっている.本論文では,検出/非検出情報に基づく分岐元信号線の単一オープン故障の診断法を述べる.検出/非検出情報は,テスタから得られる,被検査回路の故障を検出するテスト(フェイルテスト)の集合と故障を検出しなかったテスト(パステスト)の集合の情報,及びこれらのテストに対する故障シミュレーションによって得られる,仮定した故障を検出できるか否かの情報である.提案する診断法は,まず,分岐先信号線における単一縮退故障に対して,フェイルテストを用いて単一縮退故障シミュレーションを行う.その故障の検出回数に基づいて故障候補の分岐元信号線を推定する.次に,故障候補の分岐元信号線から分岐する分岐先信号線における単一縮退故障に対して,パステストを用いて単一縮退故障シミュレーションを行う.その検出回数に基づいて被検査回路に存在しないと推定される故障候補の分岐元信号線を削除する.更に,診断分解能を向上させるため,故障候補の分岐元信号線から分岐する分岐先信号線における多重縮退故障に対して,フェイルテストを用いて多重縮退故障シミュレーションを行い,その検出回数を利用して故障候補を指摘している.ISCAS'85ベンチマーク回路及びフルスキャン化されたISCAS'89ベンチマーク回路に対する実験結果では,提案した故障診断法は,ほとんどの故障回路に対して指摘した故障候補の数を5個以下にできることを示している.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Substantial attention is being paid to the fault diagnosis problem in recent test literature. Yet, the compaction of test vectors for fault diagnosis is little explored. The compaction of diagnostic test vectors must take care of all fault pairs that need to be distinguished by a given test vector set. Clearly, the number of fault pairs is much larger than the number of faults thus making this problem very difficult and challenging. The key contributions of this paper are: 1) to use techniques for reducing the size of fault pairs to be considered at a time, 2) to use novel variants of the fault distinguishing table method for combinational circuits and reverse order restoration method for sequential circuits, and 3) to introduce heuristics to manage the space complexity of considering all fault pairs for large circuits. Finally, the experimental results for ISCAS benchmark circuits are presented to demonstrate the effectiveness of the proposed methods.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

For deep-submicron technology based LSIs, conventional stuck-at fault model is no longer sufficient for fault test and diagnosis. In this paper we present a method of fault diagnosis for transistor shorts ire combinational and full-scan circuits under logic test environment. Description of a short requires a very large number of physical parameters, and hence it is difficult, if not impossible, to describe precisely the behavior of transistor shorts. Therefore, we define two types of transistor short models and we develop algorithms to address the diagnostic problem. A novelty of our algorithms is that they use conventional stuck-at fault simulation methodologies to diagnose transistor level shorts. We conduct experiments on benchmark circuits to demonstrate the effectiveness of our method.

DOI： 10.1109/ATS.2006.260955

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その他リンク： https://dblp.uni-trier.de/db/conf/ats/ats2006.html#HigamiSTKT06

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

With the increasing complexity of LSI, Built-In Self Test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore we propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We call the fault diagnosis based on the compressed responses from BIST the post-BIST fault diagnosis [12, 13]. The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 [11] benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, we can confirm the feasibility of diagnosing the large circuits within the practical CPU times. We prove the feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis.

DOI： 10.1109/DFT.2006.24

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その他リンク： https://dblp.uni-trier.de/db/conf/dft/dft2006.html#TakahashiKHTYAS06

記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

組込み自己テスト(BIST)環境においては, 検査結果として得られる出力署名が高圧縮であるため, 被検査回路の故障を検出するテスト(検出テスト)の集合として識別された検出テスト候補の集合に被検査回路の故障を検出しないテスト(非検出テスト)が誤って含まれてしまう場合がある. したがって, BIST環境で識別された検出テスト候補の集合は不確かな検出テスト集合となる. また, BIST環境では, どの外部出力において誤りを観測したかを知ることが困難である. そこで, 本論文では, BIST環境における不確かなテスト集合による単一縮退故障の診断法を提案する. 提案する故障診断法は, 誤りを観測する外部出力の位置とその故障値を診断に利用しないで, 単一縮退故障シミュレーションを用いた次の三つの手法で構成されている. (1)不確かな検出テスト集合及び非検出テスト集合で構成された不確かなテスト集合を用いた単一縮退故障シミュレーションの結果に基づいて故障候補を推定する手法, (2)不確かな検出テスト集合に誤って含まれた非検出テストの候補を推定する手法, 及び(3)単一縮退故障シミュレーションを利用して求めた故障候補の検出回数に基づいて故障候補数を削減する手法. 次に, ISCAS'85ベンチマーク回路及びフルスキャン化されたISCAS'89ベンチマーク回路に対する評価実験結果によって, 提案法が不確かなテスト集合を用いても短い処理時間で, ほとんどの故障回路に対して指摘した故障候補数を5個以下(平均故障候補数は2個程度)に抑えることができ, BIST環境における故障診断に適応可能であることを示す.

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

In this paper, we describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults.

DOI： 10.1109/TCAD.2004.837733

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

With the scaling of VLSI feature size and increasing complexity of VLSI, it is difficult to determine the cause of failure in a chip. Most of the studies on failure analysis have assumed one fault model, such as single/multiple stuck-at, bridging, or open faults. However, we do not know which fault model can explain a behavior of the defect in the circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty response on the application of a failing test. In this paper, we propose an effective diagnostic method in the presence of unknown fault model, based on only pass/fail information on the applied tests. The proposed method deduces faulty conditions that are able to explain the behavior of the defect in the circuit and locates faulty sites, based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing tests. As a result, we can derive a fault model from the faulty condition. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing tests. Experimental results show that our method can accurately identify the fault models for 93% faulty circuits and that the faulty sites are located within several candidates except for circuits with multiple stuck-at faults.

DOI： 10.1109/ISCAS.2005.1465255

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

With the scaling of VLSI feature size and increasing complexity of VLSI, it is difficult to determine the cause of failure in a chip. Most of the studies on failure analysis have assumed one fault model, such as single/multiple stuck-at, bridging, or open faults. However, we do not know which fault model can explain a behavior of the defect in the circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty response on the application of a failing test. In this paper, we propose an effective diagnostic method in the presence of unknown fault model, based on only pass/fail information on the applied tests. The proposed method deduces faulty conditions that are able to explain the behavior of the defect in the circuit and locates faulty sites, based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing tests. As a result, we can derive a fault model from the faulty condition. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing tests. Experimental results show that our method can accurately identify the fault models for 93% faulty circuits and that the faulty sites are located within several candidates except for circuits with multiple stuck-at faults.

DOI： 10.1109/ISCAS.2005.1465255

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

With the scaling of VLSI feature size and increasing complexity of VLSI, it is difficult to determine the cause of failurein a chip. Most of the studies on failure analysis have assumed one fault model, such as single/multiple stuck-at, bridging, or open faults. However, we do not know which fault model can explain a behavior of the defect in the circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty response on the application of a failing test. In this paper, we propose an effective diagnostic method in the presence of unknown fault model, based on only pass/fail information on the applied tests. The proposed method deduces faulty conditions that are able to explain the behavior of the defect in the circuit and locates faulty sites, based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing tests. As a result, we can derive a fault model from the faulty condition. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing tests. Experimental results show that our method can accurately identify the fault models for 93% faulty circuits and that the faulty sites are located within several candidates except for circuits with multiple stuckat faults. © 2005 IEEE.

DOI： 10.1109/ISCAS.2005.1465255

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

Recently, manufacturing defects including opens in the interconnect layers have been increasing. Therefore, a failure analysis for open faults has become important in manufacturing. Moreover, the failure analysis for open faults under BIST environment is demanded Since the quality of the failure analysis is engaged by the resolution of locating the fault, we propose the method for locating single open fault at a stem, based on only detecting/un-detecting information on tests. Our method deduces candidate faulty stems based on the number of detections for single stuck-at fault at each of fanout branches, by performing single stuck-at fault simulation with both detecting and un-detecting tests. To improve the ability of locating the fault, the method reduces the candidate faulty stems based on the number of detections for multiple stuck-at faults at fanout branches of the candidate faulty stem, by performing multiple stuck-at fault simulation with detecting tests.

DOI： 10.1109/ATS.2004.44

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その他リンク： https://dblp.uni-trier.de/db/conf/ats/ats2004.html#SatoTHT04

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

We have proposed a method for identifying candidate single stuck-at faults based on the ambiguous test set [9]. In this paper, we propose enhancing methods for diagnosing single/multiple stuck-at faults under BIST environment to reduce the number of candidate faults. The enhancing method uses the number of detections for candidate faults and the first detecting test to diagnose the candidate faults. Moreover, we propose an enhancing method for diagnosing multiple stuck-at faults by using test-pairs.

DOI： 10.1109/ATS.2004.41

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.2004.41

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose an alternative method that does not generate a test for each path delay fault directly to generate tests for path delay faults. The proposed method generates an N-propagation test-pair set by using an N-i-detection test set for single stuck-at faults. The N-propagation test-pair set is a set of vector pairs which contains N distinct vector pairs for every transition faults at a check point. Check points consist of primary inputs and fanout branches in a circuit. We do not target the path delay faults for test generation, instead, the N-propagation test-pair set is generated for the transition (both rising and falling) faults of check points in the circuit. After generating tests, tests are simulated to determine their effectiveness for singly testable path delay faults and robust path delay faults. Results of experiments on the ISCAS'85 benchmark circuits show that the N-propagation test-pair sets obtained by our method are effective in testing path delay faults.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

We propose a method for diagnosing single stuck-at faults under Built-In Self-Test (BIST) environment. Under BIST environment, it is difficult to determine which BIST vectors produced errors due to the high degree of test response compaction. Therefore the detecting test set that is determined in BIST session includes un-detecting tests. We call the detecting test set determined after BIST session an "ambiguous diagnostic test set". First, we propose a method for identifying candidate faults based on the ambiguous diagnostic test set. Moreover we propose a method for identifying candidate un-detecting tests that belong to the ambiguous diagnostic test set. Diagnosis by using more accurate diagnostic test set is able to improve the diagnostic ambiguity.

DOI： 10.1109/TSM.2005.1250099

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その他リンク： https://dblp.uni-trier.de/db/conf/dft/dft2003.html#TakahashiTAT03

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper we propose two diagnosis methods for crosstalk-induced pulse faults in sequential circuits using crosstalk fault simulation. These methods compare observed responses and simulated values at primary outputs to identify a set of suspected faults that are consistent with the observed responses. The first method is a restart-based method which determines the suspected fault list by using the knowledge about the first and last failures of the test sequence. The advantage of the restart-based method over a method using full simulation is its reduction of the number of simulated faults in a process of diagnosing faults. The second method is a resumption-based method which uses stored state information. The advantage of the resumption-based method over the restart-based method is its reduction of the CPU time for diagnosing the faults. The effectiveness of the proposed methods is evaluated by experiments conducted on ISCAS'89 benchmark circuits. From the experimental results we show that the number of suspected faults obtained by our methods is sufficiently small, and the resumption-based method is substantially faster than the restart-based method.

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Diagnosing multiple stuck-at faults in combinational circuits using single- and multiple-fault simulation is proposed. The proposed method adds (removes) faults from a set of suspected faults depending on the result of multiple-fault simulation at a primary output agreeing (disagreeing) with the observed value. However, the faults that are added or removed from the set of suspected faults are determined using single-fault simulation. Diagnosis is carried out by repeated addition and removal of faults. The effectiveness of the diagnosis method is evaluated by experiments conducted on benchmark circuits and it is found to be substantially superior compared to the previous known solutions. The method proposed in this paper can be used as a powerful tool at the preprocessing stage of diagnosis in an electron-beam tester environment.

DOI： 10.1109/43.986429

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

Diagnosing multiple stuck-at faults in combinational circuits using single- and multiple-fault simulation is proposed. The proposed method adds (removes) faults from a set of suspected faults depending on the result of multiple-fault simulation at a primary output agreeing (disagreeing) with the observed value. However, the faults that are added or removed from the set of suspected faults are determined using single-fault simulation. Diagnosis is carried out by repeated addition and removal of faults. The effectiveness of the diagnosis method is evaluated by experiments conducted on benchmark circuits and it is found to be substantially superior compared to the previous known solutions. The method proposed in this paper can be used as a powerful tool at the preprocessing stage of diagnosis in an electron-beam tester environment.

DOI： 10.1109/43.986429

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その他リンク： http://dblp.uni-trier.de/db/journals/tcad/tcad21.html#journals/tcad/TakahashiBST02

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

With increasing chip interconnect distances, open-interconnect is becoming an important defect. The main challenge with open-interconnects stems from its non-deterministic real-life behavior In this work, we present an efficient diagnostic technique for multiple open-interconnects. The algorithm proceeds in two phases. During the first phase, potential solution sets are identified following a model-free incremental diagnosis methodology. Heuristics are devised to speed up this step and screen the solution space efficiently. In the second phase, a generalized fault simulation scheme enumerates all possible faulty behaviors for each solution from the first phase. We conduct experiments on combinational and full-scan sequential circuits with one, two and three open faults. The results are very encouraging.

DOI： 10.1109/TEST.2002.1041865

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/TEST.2002.1041865

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

In order to generate tests for path delay faults we propose an alternative method that does not generate a test for each path delay fault directly. The proposed method generates an n-propagation test-pair set by using an N-i-detection test set for single stuck-at faults. The n-propagation test-pair set is a set of vector pairs which contains n distinct vector pairs for every transition faults at a check point (primary inputs and fanout branches in a circuit are called check points). We do not target the path delay faults for test generation, instead, the n-propagation test-pair set is generated for the transition (both rising and falling) faults of check points in the circuit, and simulated to determine their effectiveness for singly testable path delay faults and robust path delay faults. Results of experiments on the ISCAS'85 benchmark circuits show that the n-propagation test-pair sets obtained by our method are very effective in testing path delay faults.

DOI： 10.1109/PRDC.2002.1185647

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その他リンク： http://dblp.uni-trier.de/db/conf/prdc/prdc2002.html#conf/prdc/TakahashiST02

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

We propose a method of identifying a set of crosstalk induced delay faults which may need to be tested in synchronous sequential circuits. During the fault list generation 1) we take into account all clocking effects, and 2) infer layout information front the logic level description. With regard to layout constraints we introduce two methods, namely the distance based layout constraint and the cone based layout constraint. The lists of the target faults obtained by the proposed methods are substantially smaller than the sets of all possible combinations of faults.

DOI： 10.1109/ATS.2002.1181718

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.2002.1181718

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

This paper describes two methods of diagnosing crosstalk-induced pulse faults in sequential circuits using crosstalk fault simulation. These methods compare with observed responses and simulated values at primary outputs to identify a set of suspected faults that are consistent with the observed responses. In these methods, if the simulated values agree with the observed responses, then the simulated fault is added to a set of suspected faults, otherwise the simulated fault is removed from the set of suspected faults. The diagnosis methods repeat the above process for each time-frame to identify the suspected faults. The first method is a basic method which determines the suspected fault list by using the knowledge about the first and last failures of the test sequence. The second method uses state information and focuses on reducing the CPU time for diagnosing the faults. The CPU time is reduced by using stored state information to calculate the primary output values at the present time frame. Experimental results for ISCAS'89 benchmark circuits show that the number of suspected faults obtained by our methods is sufficiently small, and the second method is substantially faster than the first method.

DOI： 10.1109/ATS.2001.990260

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その他リンク： https://dblp.uni-trier.de/db/conf/ats/ats2001.html#TakahashiPHST01

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

This paper describes a method of identifying a set of crosstalk-induced delay faults which may need to be tested in synchronous sequential circuits. In this process, the false crosstalk-induced delay faults that need not (and/or can not) be tested in synchronous sequential circuits are also identify. Our method classifies the pairs of aggressor and victim lines, using topological information and timing information, to deduce a set of faults that need to be tested in a sequential circuit. Experimental results for ISCAS' 89 benchmark circuits show that the lists of the target faults obtained by the proposed method are sufficiently smaller than the sets of all possible combinations of faults.

DOI： 10.1109/TEST.2001.966675

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/TEST.2001.966675

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

A technique for signature based diagnosis using windows of different sizes is presented It allows to obtain increased diagnostic information from a given test at a lower cost, without additional hardware. Existing techniques that use signature based methods are limited by occurrences of aliasing that can lead to failure in the diagnosis process. The new approach proposed in this paper uses windows of different sizes based on the distribution of faults in a circuit and reduces the probability of aliasing in a window. Signature analysis can then give reliable information about failing and non-failing vectors. The effectiveness of the proposed method is evaluated by experiments conducted on ISCAS benchmark circuits. The results show that the proposed method call improve the diagnostic resolution and can reduce the cost of diagnosis.

DOI： 10.1109/ICVD.2001.902690

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その他リンク： https://dblp.uni-trier.de/db/conf/vlsid/vlsid2001.html#ClouqueurEST01

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記述言語：英語   出版者・発行元：一般社団法人電子情報通信学会  

In this paper, we consider the design for testability of multiplier based on the modified Booth Algorithm. First, we present a basic array implementation of the multiplier. Next, we introduce testability considerations to derive two C-testable designs. The first of the designs is C-testable under the single stuck-at fault model(SAF)with 10 test patterns. And, the second is C-testable under the cell fault model(CFM)with 33 test patterns.

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we consider the design for testability of a multiplier based on the modified Booth Algorithm. First, rye present a basic array implementation of the multiplier. Next. we introduce testability considerations to derive two C-testable designs. The first of the designs is C-testable under the single stuck-at fault model (SAF) with 10 test patterns. And, the second is C-testable under the cell fault model (CFM) with 33 test patterns.

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掲載種別：研究論文（学術雑誌）   出版者・発行元：IEEE Computer Society  

DOI： 10.1109/VTEST.2000.843842

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/VTEST.2000.843842

記述言語：英語   出版者・発行元：一般社団法人電子情報通信学会  

In our previous paper [9] we presented a pathtracing method of multiple gate delay fault diagnosis in combinational circuits. In this paper, we propose an improved method that uses the ambiguous delay model. This delay model makes provision for parameter variations in the manufacturing process of ICs. For the effectiveness of the current method, we propose a timed 8-valued simulation and some new diagnostic rules. Furthermore, we introduce a preparatory process that speeds up diagnosis. Also, at the end of diagnosis, additional information from the results of the preparatory process makes it possible to distinguish between non-existent faults and undiagnosed faults.

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In our previous paper [9] we presented a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. In this paper, we propose an improved method that uses the ambiguous delay model. This delay model makes provision for parameter variations in the manufacturing process of ICs. For the effectiveness of the current method, we propose a timed 8-valued simulation and some new diagnostic rules. Furthermore, we introduce a preparatory process that speeds up diagnosis. Also, at the end of diagnosis, additional information from the results of the preparatory process makes it possible to distinguish between non-existent faults and undiagnosed faults.

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記述言語：英語   出版者・発行元：一般社団法人電子情報通信学会  

A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not [1]. The latest transition time at the primary output is changed linearly with the size of the gate delay fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

A. Chatterjee et al. proposed tests with linearity property for gate delay faults to determine, at a required clock speed, whether a circuit under test is a marginal chip or not [1]. The latest transition time at the primary output is changed linearly with the size of the gate delay Fault when the proposed test is applied to the circuit under test. To authors' knowledge, no reports on an algorithmic method for generating tests with linearity property have been presented before. In this paper, we propose a method for generating tests with linearity property for gate delay faults. The proposed method introduces a new extended timed calculus to calculate the size of a given gate delay fault that can be propagated to the primary output. The method has been applied to ISCAS benchmark circuits under the unit delay model.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

ゲート遅延故障シミュレーションを用いた組合せ回路の単一ゲート遅延故障に対する一診断法を提案する. 本論文では, 一つ以上の外部出力で誤り出力を観測する誤りテスト及びすべての外部出力で正常出力を観測する正常テストを用いる。誤りテストによるゲート遅延故障シミュレーションを用いた診断法では, 誤り出力に基づいて被疑故障を推定し, また, 正常出力に基づいて存在しないと推定される故障を指摘する. 更に, 正常テストによるゲート遅延故障シミュレーションを用いて存在しないと推定される故障を指摘し, 存在しないと推定される故障を被疑故障集合から取り除く。最後に, 本診断法をISCAS'85ベンチマーク回路に適用した実験結果を示す. 本診断法は, 後方経路追跡及びゲート遅延故障シミュレーションの結果に基づく簡単な処理によって短い処理時間で診断解を得ることができる.

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掲載種別：研究論文（学術雑誌）  

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

In this paper, we propose a new method that uses single and multiple fault simulations to diagnose multiple stuck-at faults in combinational circuits. On the assumption that all suspected faults are equally likely in, the faulty circuit, multiple fault simulations are performed. Depending on, whether or not a multiple fault simulation results in primary output values that agree with the observed values, faults are added to or removed from a set of suspected faults. Faults which are to be added to or removed from the set of suspected faults are determined using single fault simulation. Diagnosis is effected by repeated additions and removals of faults. The effectiveness of the method of diagnosis has been evaluated by experiments conducted on benchmark circuits. The proposed method achieves a small number of suspected faults by simple processing. Thus, the method will be useful as a preprocessing stage of diagnosis using the electron-beam tester.

DOI： 10.1109/VTEST.1999.766648

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/VTEST.1999.766648

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）  

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記述言語：英語   出版者・発行元：一般社団法人電子情報通信学会  

Testing for delay faults is very important in the verification of the timing behavior of digital circuits. When a circuit which is unable to operate at the desired clock speed is identified, it is necessary to locate the delay fault(s)affecting the circuit in order to remedy the situation. In this paper, we present a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. We first present the basic rules for deducing suspected faults based on the multiple gate delay fault assumption. Next, in order to improve diagnostic resolution, we introduce rules for deducing non-existent faults based on the fault-free responses at the primary outputs. Using these rules, we present the detailed method for diagnosing multiple delay faults based on paths sensitized by test-pairs generated for marginal delays and gate delay faults[7]. Finally, we present results obtained from experiments on the ISCAS'85 benchmark circuits. The experimental results show the effectiveness of our method.

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

Testing for delay faults is very important in the verification of the timing behavior of digital circuits. When a circuit which is unable to operate at the desired clock speed is identified. it is necessary to locate the delay fault(s) affecting the circuit in order to remedy the situation. In this paper, we present a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. We first present the basic rules for deducing suspected faults based on the multiple gate delay fault assumption. Next, in order to improve diagnostic resolution, we introduce rules for deducing non-existent faults based on the fault-free responses at the primary outputs. Using these rules, we present the detailed method for diagnosing multiple delay faults based on paths sensitized by test-pairs generated for marginal delays and gate delay faults [7]. Finally, we present results obtained from experiments on the ISCAS'85 benchmark circuits. The experimental results show the effectiveness of our method.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

In this paper, we propose a method of diagnosing gate delay faults using delay fault simulation. rn the method, suspected faults are deduced by fault simulation and backward path-tracing using diagnostic test-pairs with observed faulty responses. Also, by fault simulation using diagnostic test-pairs with fault-free responses, non-existent faults are deduced, and they are removed from the set of suspected faults. Finally, we present experimental results on the ISCAS'85 benchmark circuits. The Experimental results show that by simple processes of backward path-tracing and fault simulation, this method achieves reasonable diagnostic resolutions in a short time.

DOI： 10.1109/ATS.1998.741599

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その他リンク： https://dblp.uni-trier.de/db/conf/ats/ats1998.html#TakahashiBT98

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE COMPUTER SOC  

In this paper, we propose an Electron Beam tester (EB-tester) aided fault diagnosis for combinational and sequential circuits based on sensitized paths. For combinational circuits, we enhance the previous set of sensitizing input pairs[1] and present EB-tester aided fault diagnosis. For sequential circuits, we introduce a measure for selecting internal lines to be probed and present EB-tester aided fault diagnosis. Experimental results of ISCAS'85 and ISCAS'89 benchmark circuits show the efficiency of the presented methods.

DOI： 10.1109/ATS.1998.741619

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その他リンク： https://dblp.uni-trier.de/db/conf/ats/ats1998.html#YanagidaTT98

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：John Wiley and Sons Inc.  

This paper proposes a method for detecting delay faults of gates in a combinational logic circuit. Assuming that a gate of the circuit has a small delay (a unit delay), the generation of a test for the circuit is described. This paper also describes the generation of the timed seven-valued calculus used in the method. The method has been applied successfully to benchmark circuits having unit delay and a fanout weighted delay. The experimental results show that the method has high fault coverage in all the circuits, and that this can be applied to the detection of gross delay faults. The proposed test method is called the 'SD test'. © Scripta Technica, Inc.

DOI： 10.1002/(SICI)1520-684X(19970615)28:6<68::AID-SCJ8>3.0.CO;2-K

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper presents a method of multiple fault diagnosis in sequential circuits by input-sequence pairs having sensitizing input pairs. We, first, introduce an input-sequence pair having sensitizing input pairs to diagnose multiple faults in a sequential circuit represented by a combinational array model. We call such input-sequence pair the sensitizing sequence pair in this paper. Next we describe a diagnostic method for multiple faults in sequential circuits by the sensitizing sequence pair. From a relation between a sensitizing path generated by a sensitizing sequence pair and a subcircuit, the proposed method deduces the suspected faults for the subcircuits, one by one, based on the responses observed at primary outputs without probing any internal line. Experimental results show that our diagnostic method identifies fault locations within small numbers of suspected faults.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：I E E E, COMPUTER SOC PRESS  

In this paper, we propose an algorithmic method for generating a test for marginal delays([1]) and gate delay faults, called an MD test. The time at which the MD test activates the latest transition at the primary output changes linearly with the size of the target delay. (1) The MD tests determine at a given clock rate (observation time) whether a circuit under test is marginal chip or not. (2) The MD tests determine the maximum circuit clock speeds. (3) The MD test detects the target gate delay fault regardless of the size of the fault by comparing the latest transition time at the primary output of the fault-free circuit and that of the faulty circuit. In order to determine the detectable size of gate delay faults, the proposed method introduces a new extended timed calculus which calculates both the latest transition time at the line in the fault-free circuit and the transition time at the same line affected by a gate delay fault of maximum fault size. We also demonstrate experimental results for gate delay faults on ISCAS benchmark circuits to show the performance of our method.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：I E E E, COMPUTER SOC PRESS  

In this paper, we consider the design for testability of multipliers based on the modified Booth Algorithm. We introduce two basic array implementations of the multiplier and present a strategy to design for c-testability. Using the proposed strategy we present two designs. The first design, which requires two primary test inputs, is c-testable under the single stuck fault model (SSF) with 17 test vectors. Also under the cell fault model (CFM) we present a design derived from the second implementation. This design, which requires only one primary test input, is c-testable with 34 test vectors and each of its cells can be tested by exhaustively applying cell input patterns.

DOI： 10.1109/ATS.1997.643914

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643914

記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：I E E E, COMPUTER SOC PRESS  

In this paper, we propose an algorithmic method for generating a test for marginal delays([1]) and gate delay faults, called an MD test. The time at which the MD test activates the latest transition at the primary output changes linearly with the size of the target delay. (1) The MD tests determine at a given clock rate (observation time) whether a circuit under test is marginal chip or not. (2) The MD tests determine the maximum circuit clock speeds. (3) The MD test detects the target gate delay fault regardless of the size of the fault by comparing the latest transition time at the primary output of the fault-free circuit and that of the faulty circuit. In order to determine the detectable size of gate delay faults, the proposed method introduces a new extended timed calculus which calculates both the latest transition time at the line in the fault-free circuit and the transition time at the same line affected by a gate delay fault of maximum fault size. We also demonstrate experimental results for gate delay faults on ISCAS benchmark circuits to show the performance of our method.

DOI： 10.1109/ATS.1997.643977

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.1997.643977

記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

一般に回路を構成するゲートはある遅延時間を有するので,その回路内部の信号線および回路の外部出力の信号値はある信号伝搬時間の後に安定する.そこで本論文では,従来の縮退故障に対する診断法においては利用されていない信号伝搬時間を利用した多重縮退故障の診断法を考察する.本論文では,各ゲートに一定の遅延を仮定した組合せ回路のもとで,ある信号線に生起された信号変化がいずれかの外部出力の信号変化の最終変化時刻を決定するような入力対を診断用テストとして提案し,その診断用テストを用いた診断法を述べる.本論文で述べる診断法は,診断用テストを与えた回路の外部出力で観測される信号値だけでなく信号変化の最終変化時刻を診断に利用して故障候補を推定する.次に,信号伝搬時間を考慮した時間付き前方操作を用いた診断法を述べる.最後に,ベンチマーク回路に本診断法を適用した実験を行い,本診断法の有効性を示す.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

各ゲートに一定の遅延を仮定した組合せ回路を考える. 本論文では, この回路の一つの目標信号線における微小なゲート遅延故障を検出するテストを提案し, その生成法を述べる. ここで, 微小なゲート遅延故障とは目標の信号線に付加した1単位付加遅延であり, 提案するテスト(SD (Small gate Delay fault)テストと呼ぶ)は, 回路の各ゲートに仮定した遅延のもとでその1単位付加遅延を検出することができる. 次に, 変化信号値の伝搬遅延時間を導入した時間付き7値演算を用いて, 目標の信号線に対するSDテストの生成法を述べる. 最後に, その生成法を1単位遅延およびファンアウト重み付き遅延を各ゲートに仮定したベンチマーク回路に適用して実験を行い, すべての回路に対して高い検出率をもつSDテストが生成できること, またSDテストは大きなゲート遅延故障に対しても有用であることを示している.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：I E E E, COMPUTER SOC PRESS  

This paper presents a new approach to multiple fault diagnosis in sequential circuits by using input-sequence pairs having sensitizing input pairs. This represents an extension of our previous work dealing with combinational circuits. After reviewing our previous method, first, we introduce an input-sequence pair having sensitizing input pairs to diagnose multiple faults in a sequential circuit partitioned into subcircuits. We call such input-sequence pair the sensitizing sequence pair in this paper. Next, we extend the use of the previous method for combinational circuits to sequential circuits. From a relation between a sensitizing path generated by a sensitizing sequence pair and a subcircuit, the proposed method deduces the suspected faults for the subcircuits, one by one, based on the responses observed at primary outputs without probing any internal line. This paper provides the first experimental reports on diagnostic results of the ISCAS circuits by using our diagnostic method for sequential circuits, without probing and internal line, any fault simulation, or fault enumeration.

DOI： 10.1109/FTCS.1996.534597

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/FTCS.1996.534597

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRON INFO COMMUN ENG  

Some undetectable stuck-at faults called the redundant faults are included in practical combinational circuits. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit such as increase of delay time and decrease of testability of the circuit. It is considered that some redundant faults may cause the logical defects in the future. In this paper, firstly, we study the testability of the redundant fault in the combinational circuit by using delay effects. Secondly, we propose a method for generating a test-pair of a redundant fault by using an extended seven-valued calculus, called TGRF (Test-pair Generation for Redundant Fault). TGRF generates a dynamically sensitizable path for the target line which propagates the change in the value on the target line to a primary output. Finally, we show experimental results on the benchmark circuits under the assumptions of the unit delay and the fanout weighted delay models. It shows that test-pairs for some redundant faults are generated theoretically.

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その他リンク： http://dblp.uni-trier.de/db/journals/ieicet/ieicet78d.html#journals/ieicet/YuTT95

記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：SCRIPTA TECHNICA PUBL  

This paper presents a new method for multiple fault diagnosis of combinational circuits using sensitizing input-pairs. A partition of a circuit under test into subtree circuits and a generation method for diagnostic test are described. The set of diagnostic tests used in this paper is one of sensitizing input-pairs that generate sensitizing paths including checkpoints on them.
By studying the relation between a sensitizing path generated by a sensitizing input-pair and a subtree circuit, a method is presented for multiple fault diagnosis in the subtree circuit based on the fault-free and the faulty responses observed at primary outputs. A deduction algorithm is described for a value at an output of a,subtree circuit which does not have a primary output. The proposed method is applied to benchmark circuits having double faults, triple faults, and fourfold faults. Experimental results show that suspected faults are identified within 8 to 30 percent of all stuck-at 0 and 1 faults on all lines in the circuit.

DOI： 10.1002/scj.4690260302

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掲載種別：研究論文（学術雑誌）  

DOI： 10.1109/MDT.1995.466375

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その他リンク： http://dblp.uni-trier.de/db/journals/dt/dt12.html#journals/dt/YanagidaTT95

掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE Computer Society  

DOI： 10.1109/ATS.1995.485357

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その他リンク： http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485357

掲載種別：研究論文（国際会議プロシーディングス）  

DOI： 10.1109/ATS.1995.485317

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その他リンク： https://dblp.uni-trier.de/db/conf/ats/ats1995.html#TakahashiYT95

記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

本論文では,組合せ回路を部分樹状回路に分割し,それらの構造記述関数(EFF)を結合した新しいEFF表現(拡張EFF)を導入した.次に拡張EFFの経路微分を用いて回路の単一経路を活性化性に関して四つに分類した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

組合せ回路の多重縮退故障に対する活性入力対を用いた新しい診断法を提案する.まず,故障診断のための回路の部分樹状回路への分割について述べ,次に診断テスト集合の生成法について述べる.本論文の診断テスト集合は,回路の検査点をその活性化経路上に含む活性化入力対の集合である.診断テスト集合の要素である活性化入力対が作る活性化経路と部分樹状回路との関係を考察し,外部出力において正常値が観測されたとき,および誤りが観測されたときの部分樹状回路の診断法を示す.次に,外部出力をもたない部分樹状回路の故障診断のため,その出力の推定法を述べる.最後に,本論文で提案する診断法をベンチマーク回路の2,3,および4重故障に対して適用する.その実験結果は全故障数の8〜30%の範囲に被疑故障箇所を推定することができることを示している.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

We present two techniques for improving the efficiency of the previous method for multiple fault diagnosis of combinational circuits[1]. (1) Three new rules for deducing the values at the internal lines are added to the previous deduction rules. Experimental results show that 2.6approx.15.2% improvements in resolution are achieved by adding the enhanced deduction rules without probing the internal lines. (2) A probing method for diagnosis is proposed to improve the resolution obtained by the method (1). Preliminary experimental results show that about 0.1approx.9.4% improvements in resolution are further achieved by probing about 4approx.111 internal lines in the circuit.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：IEEE  

Practical combinational circuits include some undetectable stuck-at faults called the redundant faults. The redundant fault does not affect the functional behavior of the circuit even if it exists. The redundant fault, however, causes undesirable effects to the circuit such as increase of delay time and decrease of testability of the circuit. It is considered that some redundant faults may cause the logical defects in the future. In this paper, we study the testing problem of the redundant fault in the combinational circuit by using delay effects and propose a method for generating a test-pair of a redundant fault. By using an extended seven-valued calculus, the proposed method generates a dynamically sensitizable path which includes a target redundant fault on a restricted single path. The dynamically sensitizable path will propagate the effect of the target redundant fault to the output of the circuit by the delay effects. Preliminary experiments on the benchmark circuits show that test-pairs for some redundant faults are generated theoretically.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

7値を用いて生成した部分単一活性化経路^(1)>に基づく組合せ回路における多重縮退故障の一診断法を提案する.本稿の診断テスト集合は検査点を部分単一活性化経路に含むような活性化経路を作る活性化入力対の集合である.本診断法はまず,外部出力で故障出力が観測された診断テスト対により生成される活性化経路に沿って,故障候補の集合を推定する.次に,外部出力で正常出力が観測される診断テスト対で生成される活性化経路に沿って,故障候補の一つが他の故障候補の存在に関わらず外部出力までの変化信号値の伝搬を阻止するかを判定する.このような伝搬を阻止する故障を前述の故障候補の集合から除くことにより,故障箇所の絞り込みを行うという手法である.この手法を2重故障,3重故障,および4重故障を仮定したベンチマーク回路に適用した結果は,回路の内部信号線を観測することなく,故障箇所を全故障数の0.7〜24.0%,2.2〜23.2%,および2.5〜25.7%の範囲に,それぞれ推定することができることを示している.

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記述言語：日本語   出版者・発行元：電子情報通信学会  

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記述言語：英語   掲載種別：研究論文（学術雑誌）   出版者・発行元：IEICE-INST ELECTRON INFO COMMUN ENG  

The single fault model is invalid in many cases. However, it is very difficult to generate tests for all multiple faults since an m-line circuit may have 3m - 1 multiple faults. In this paper, we describe a method for generating tests for combinational circuits with multiple stuck-at faults. An input vector is a test for a fault on a target line, if it find the target line to be fault-free in the presence of undetected or undetectable lines. The test is called a robust test for fault on a target line. It is shown that the sensitizing input-pair for a completely single sensitized path can be a robust test-pair. The method described here consists of two procedures. We label these as "SINGLE SEN" procedure and "DECISION" procedure. SINGLE SEN generates a single sensitized path including a target line on it by using a PODEM-like method which uses a new seven-valued calculus. DECISION determines by utilizing the method proposed by H. Cox and J. Rajski whether the single sensitizing input-pair generated by the SINGLE SEN is a robust test-pair. By using these two procedures the described method generates robust test-pairs for the combinational circuit with multiple stuck-at faults. Finally, we demonstrate by experimental results on the ISCAS85 benchmark circuits that SINGLE SEN is effective for an algorithmic multiple fault test generation for circuits not including many XOR gates.

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記述言語：英語   掲載種別：研究論文（国際会議プロシーディングス）   出版者・発行元：Institute of Electrical and Electronics Engineers Inc.  

A test generated under the single-fault assumption may be invalid for the combinational circuit with multiple faults for the sake of masking among them. In this paper, we propose a new test generation algorithm for combinational circuits with multiple faults. A property of a valid test which can detect a target fault regardless of the presence of any other fault is studied and it is shown that a pair of input vectors is necessary for the valid test of a target fault. Next, a new algorithm for generating a single sensitized path using a sevenvalued calculus and a decision algorithm for finding a completely single sensitized path are presented. Finally, experimental results on several benchmark circuits are given.

DOI： 10.1109/RFTS.1991.212943

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記述言語：日本語   出版者・発行元：愛媛大学大学教育総合センター  

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担当区分：責任著者   記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）   出版者・発行元：一般社団法人エレクトロニクス実装学会  

次世代のIoTエッジデバイス向けのメモリベース論理再構成デバイスMRLD(Memory-based Reconfigurable Logic Device）では，IoTシステムとしての高信頼性を保証するために，運用中に劣化状態を早期に検知・報告する劣化障害予告技術が求められる．本研究では，MRLDデバイスの構成要素であるLUTでの経年劣化による遅延を計測するために，MRLDデバイスの構造に適した遅延計測論理回路用リングオシレータを設計し，その実装方法を提案する。さらに，論理シュミレーションによって提案法の有効性を評価する。

DOI： 10.11486/ejisso.34.0_4c1-02

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担当区分：最終著者,　責任著者   記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

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担当区分：最終著者,　責任著者   記述言語：日本語  

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記述言語：日本語   出版者・発行元：電子情報通信学会  

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掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

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記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）   出版者・発行元：一般社団法人 日本機械学会  

DOI： 10.1299/jsmetld.2018.27.2307

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

DOI： 10.5104/jiep.21.405

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その他リンク： http://id.ndl.go.jp/bib/029502573

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

DOI： 10.11486/ejisso.32.0_18

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鉄道信号設備は，安全性と信頼性の確保が不可欠な重要設備であり，鉄道会社は設備の維持に毎年多くの労力と費用を費やしている．しかしながら，近年の少子高齢化により鉄道利用者の減少による収入減が想定されており，設備のライフサイクルコストの低減が求められている．そこで本論文では，従来の鉄道信号設備のライフサイクルコストモデルに「設備故障が旅客に与える経済的損失コスト」を考慮した新たなモデルを提案する．その上で代表的な鉄道信号設備である軌道回路に対して，経済的損失コストを評価尺度とした保全計画の策定や設備故障の原因分析を行う．そして，分析に基づく改善対策によって，設備のライフサイクルコストが低減できることを示す．

DOI： 10.14923/transinfj.2015jdp7085

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

テスト時の過剰のIRドロップ(瞬時電圧降下)による抵抗性オープン故障診断の結果が誤診断となる問題がある。本稿では、既存の抵抗性オープン故障の検出パターンからIRドロップの低い診断用パターンを選択する手法を提案する.提案手法は,抵抗性オープン故障の最長活性化経路と励起条件を維持しながらドントケア抽出を行い,ドントケア埋め込みによって診断用パターンを求める.効果的なIRドロップ低減を実現するため,焼きなまし最適化アルゴリズムをベースにしたドントケア埋め込み手法を提案する.実験結果より、提案手法によってIRドロップが低減できることを示す。

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© (2014) by Society of Digital Information and Wireless Communication (SDIWC). All rights reserved. The spread of the Internet has introduced many online government forms and electronic commerce applications using standard forms defined in the XML format. In case of fields that require specialized knowledge of a certain field, it is important not only to verify XML format but also to verify the validity of the form or transaction data before transmission. In this paper, we propose a validation system to perform verification on the basis of the XML document content. The feature of the proposed system is to construct ontologies using OWL, SWRL and extended rules. And it is to execute reasoning using these ontologies to judge the validity of the document content. To demonstrate usefulness in a use case of the proposed method, we present a validation system for a Japanese real property registration application.

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記述言語：日本語   出版者・発行元：一般社団法人エレクトロニクス実装学会  

最近，VLSIの故障検査に関する国際会議においても，３次元VLSIの故障検査法に関する研究は注目されている．しかしながら，３次元VLSIの故障検査法はいまだ確立されていないのが現状である．そこで，本発表では，３次元VLSIに対する故障検査法の研究動向を整理する．まず，従来のVLSIに対する検査容易化設計法（バンダリースキャン設計，SoC向け検査容易化設計）の適用可能性について述べる．つぎに，３次元VLSIの貫通ビア(TSV)に対する故障検査の問題を言及する．最後に，TSVの故障に対するテストパターン生成法について述べる．

DOI： 10.11486/ejisso.28.0_231

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記述言語：英語   出版者・発行元：IEEE  

In this paper, we propose a new method that can measure the resistance of high density post-bond TSVs including serial micro-bumps and bond resistance. The key idea of the proposed technology is to use Electrical Probe embedded in the stacked silicon dies. It is a measuring circuit based on Analog Boundary-Scan (IEEE1149.4). We modify the standard Analog Boundary-Scan structure to realize the high measuring accuracy for TSVs in 3D-SIC. The main contribution of the method is to measure the resistance of high pin count (e.g. &gt; 10,000) post-bond TSVs accurately. Electrical Probes correspond to the high density of TSV (e.g. &lt; 40 um pitch) and work like as Kelvin probe. The measurement accuracy is less than 10 m Omega. We also introduce the preliminary results of small scale measuring experiments and the results of SPICE simulation of large scale measuring circuits.

DOI： 10.1109/ICEP.2014.6826673

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記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

J-GLOBAL

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記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

J-GLOBAL

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記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

J-GLOBAL

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記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

J-GLOBAL

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記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

J-GLOBAL

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記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

J-GLOBAL

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記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

J-GLOBAL

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記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

J-GLOBAL

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記述言語：日本語   掲載種別：研究発表ペーパー・要旨（全国大会，その他学術会議）  

J-GLOBAL

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記述言語：日本語   出版者・発行元：電子情報通信学会  

CiNii Books

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

本研究では,電磁界シミュレーションおよび半断線故障TEGの製作・測定に基づいてシグナルインティグリティ不良の原因となる配線の半断線故障の振る舞いを解明する.さらに,得られた解析結果に基づいて半断線故障に対する故障検査法を提案する.これらの研究成果は,2009年度から2011年度に行った(株)半導体理工学研究センター(STARC)との共同研究成果である.

CiNii Books

CiNii Research

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

新技術の発展や国際条約に対応する為、日本の著作権法は過去に何度か改正されてきた。しかし現状の著作権法では様々な放送伝達方法に対応が出来ないと考える。中でもIPマルチキャスト放送に着目する。サービス内容等がほぼ同一であっても現著作権法ではIPマルチキャスト放送は「自動公衆送信」、CATVは「有線放送」と区分されている。近年、著作権法改正したイギリスではIPマルチキャスト放送とCArvの区分を無くし柔軟な法律体系をとっている。研究結果からの提案は諸外国著作権法の結果を軸とし、IPマルチキャスト放送、有線放送、放送の区分を廃止、統合する著作権法改正である。提案により様々な技術的ニーズに応えられると期待できる。

CiNii Books

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

エレクトロニクス製品の小型高機能化に伴い実装プリント板の高密度化が増々進んでおり,実装不良を容易に検出できるバウンダリスキャンテストが必要不可欠になりつつある.バウンダリスキャンテストは,これまでLSI間の相互接続テストに関して論じられることが多かったが,今回筆者らはバウンダリスキャンテスト中のLSIの内部回路の挙動を分析し,テスト上の課題について考察した.

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

エレクトロニクス製品の小型高機能化に伴い実装プリント板の高密度化が増々進んでおり,実装不良を容易に検出できるバウンダリスキャンテストが必要不可欠になりつつある.バウンダリスキャンテストは,これまでLSI間の相互接続テストに関して論じられることが多かったが,今回筆者らはバウンダリスキャンテスト中のLSIの内部回路の挙動を分析し,テスト上の課題について考察した.

CiNii Books

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記述言語：英語   出版者・発行元：Institute of Electronics, Information and Communication, Engineers, IEICE  

In this paper, we propose a test generation method for diagnosing transition faults. The proposed method assumes launch on capture test, and it generates test vectors for given fault pairs using a stuck-at ATPG tool so thst they can be distinguished. If a given fault pair is in-distinguishable, it is identified, and thus the proposed method achieves a complete diagnostic test generation. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at-fault, and some additional logic gates are inserted in a CUT during the test generation process. Experimental results show that the proposed method can generation process. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguised by commercial tools, and also identify indistinguishable fault pairs. Copyright © 2012 The Institute of Electronics, Information and Communication Engineers.

DOI： 10.1587/transinf.E95.D.1093

Scopus

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記述言語：日本語   出版者・発行元：一般社団法人電子情報通信学会  

DOI： 10.1587/ieiceissjournal.17.3_13

CiNii Research

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記述言語：日本語  

J-GLOBAL

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記述言語：日本語  

J-GLOBAL

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記述言語：日本語  

J-GLOBAL

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記述言語：日本語  

J-GLOBAL

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