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DOI： 10.1109/DFT59622.2023.10313532

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Other Link： https://dblp.uni-trier.de/db/conf/dft/dft2023.html#WangWMKHTSWN23

Publishing type：Research paper (international conference proceedings)  

Identifying optimal test points to maximize fault coverage is crucial for improving field tests of large-scale integrated circuits (LSIs). In this paper, we introduce Deep-TPs-Explorer, a method that utilizes deep graph-convolutional neural networks (GCNs) to identify a more effective set of test points, thereby enhancing the random testability of logic circuits. For efficient training of the GCN, we employ the Advantage Actor-Critic (A2C) reinforcement learning algorithm. The effectiveness of our proposed method is validated using the ISCAS89 and ITC99 benchmark circuits.

DOI： 10.1109/ITC-CSCC58803.2023.10212888

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Test point insertion is an effective approach for improving fault diagnosis ability as well as testability. This paper presents a test points, as observation points, insertion for improving fault diagnosis ability. In order to find suitable observation points, scores are calculated on signal lines for each fault pair that is not distinguished by the given test set. After selecting observation points, the proposed method partitions primary outputs and the inserted observation points into groups such that the output responses in the same group are compacted by XOR operation. The partition method allows to reduce the number of values to be observed without decreasing the diagnosis ability. The effectiveness of the proposed method is validated by experiments on benchmark circuits.

DOI： 10.1109/ITC-CSCC58803.2023.10212844

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Publishing type：Research paper (scientific journal)   Publisher：Association for Computing Machinery (ACM)  

Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST). Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method.

DOI： 10.1145/3563552

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Authorship：Lead author   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/itc-cscc55581.2022.9894966

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Authorship：Lead author   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/itc-cscc52171.2021.9501474

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

In this paper, we display a preliminary evaluation of some artificial neural networks (ANNs) that are used as test pattern generators (TPGs) for the BIST technology. In the evaluation, fault coverages of test patterns by ANN- TPGs and numbers of transistors required for those TPGs are compared with those of LFSRs and ROMs. Computational results display that ANN- TPGs with sufficient hidden nodes can yield higher fault coverages than LFSRs with fewer transistors than ROMs.

DOI： 10.1109/ITC-CSCC52171.2021.9501263

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Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/itc-cscc52171.2021.9501454

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Authorship：Last author   Language：English   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electronics, Information and Communications Engineers (IEICE)  

DOI： 10.1587/transfun.2020vlp0007

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

In this paper, we display an approach to detect circuit faults by the built-in self test (BIST) technology. In the BIST for a certain circuit, it is usual to generate test patterns by feeding their seed values to a test pattern generator (TPG), which is contained in a device together with the circuit. It is ideal but impractical to make the device to contain a digital memory that stores effective test patterns. The key idea of the presented approach is to use the artificial neural network (ANN) as such memory on the expectation that an ANN can be implemented as an analog circuit. In addition, this paper investigates the inaccuracy that is inevitable regarding analog components.

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CiNii Research

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MRLD is a new type of reconfigurable device constructed by general SRAMs array that is promising to use for the next-generation IoT edge devices. During the operation of the MRLD, aging-induced failures may occur without any previous notice, which greatly affects the reliability of the entire IoT systems. In this paper, we propose a method for early detecting and reporting the effect of the aging in MRLD. The method configures a new designed ring oscillator circuit into the MRLD for monitoring its internal delay variations. Simulation results confirmed the effectiveness of the proposed method.

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Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1587/transinf.2019EDP7235

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Other Link： https://dblp.uni-trier.de/db/journals/ieicetd/ieicetd103.html#Al-AwadhiAWHTIM20

Language：Japanese  

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

When a system is in idle/starting-up state, Field-Testing is a promising way to guarantee the reliability of an advanced system. However, the extremely limited test application time obstructs the implementation of field test. In this paper, we introduce a test pattern partitioning approach by using two well-known machine learning algorithms: Simulated Annealing (SA) and Support Vector Machines (SVM), to derive an optimal solution for pattern partitioning that minimizes the test latency for high reliability. From the experimental results on benchmark circuit we show that both SA and SVM based method can significantly improve the test latency of partition test, and SVM is much more efficient than SA. Those results confirm the feasibility of machine learning algorithm for the pattern partition problem.

DOI： 10.1109/ITC-CSCC.2019.8793328

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Field testing and field diagnosis are effective ways for achieving high reliability of modern systems. Since they are executed during an idle mode or a start-up mode in a system, they must be completed within very short time. Adaptive diagnosis applies test patterns selectively according to a candidate faults set that is obtained during the fault diagnosis process. In this paper, we propose an adaptive fault diagnosis method using a compact dictionary in order to reduce compute time for deducing candidate faults. A compact dictionary is created by compacting some output values into one bit. Although the compute time is reduced using a compact dictionary, the number of applied test patterns for diagnosis may increase in some cases. We investigate the relation between the size of a compact dictionary, compute time and the number of test patterns by experiments for benchmark circuits.

DOI： 10.1109/ITC-CSCC.2019.8793429

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

This study displays preliminary results on a simple technique to improve fault coverages in the BIST technology. The technique assumes that a circuit which implements an ANN can be used with the target circuit, and effective test patterns are given beforehand. Such ANN circuit is utilized as a degraded memory which approximately regenerates given test patterns. In computational illustrations, fault coverages of test patterns by the technique are calculated on c7552 of the ISCAS'85 benchmark.

DOI： 10.1109/ITC-CSCC.2019.8793374

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CiNii Research

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

DOI： 10.1109/ATS.2017.16

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Other Link： https://dblp.uni-trier.de/db/conf/ats/ats2017.html#WangHTSKS17

Language：English   Publishing type：Research paper (scientific journal)  

DOI： 10.1007/s40595-018-0117-9

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

Recently, reconfigurable devices are gaining increased attention for the development of IoT, Automotive and AI system. A new type of fine-grained reconfigurable device named MRLD (Memory Based Reconfigurable Logic Device) has been proposed which is constructed by general SRAMs without any programmable interconnect resources. It should be a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In this paper, we overview the architecture and the operation principle of MRLD. We also propose a test strategy and algorithms of pattern generation for the interconnect defects referred to stuck-at and bridge faults under MRLD. Experimental results confirmed the effectiveness of the proposed test method.

DOI： 10.1109/ATS.2017.16

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DOI： 10.1109/MDAT.2018.2799801

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/ETS.2018.8400707

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

DOI： 10.1109/ATS.2018.00038

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electronics, Information and Communication, Engineers, IEICE  

Small delay caused by a resistive open is difficult to test since circuit delay varies depending on various factors such as process variations and crosstalk even in fault-free circuits. We consider the problem of discriminating a resistive open by anomaly detection using delay distributions obtained by the effect of various input signals provided to adjacent lines. We examined the circuit delay in a fault-free circuit and a faulty circuit by applying electromagnetic simulator and circuit simulator for a line structure with adjacent lines under consideration of process variations. The effectiveness of the method that discriminates a resistive open is shown for the results obtained by the simulation.

DOI： 10.1587/transfun.E100.A.2842

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electronics, Information and Communication, Engineers, IEICE  

In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.

DOI： 10.1587/transinf.2016EDL8210

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.

DOI： 10.1587/transinf.2016EDL8210

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper, the authors propose an integer linear programming (ILP) model for static multi-car elevator operation problems. Here, "static" means that all information which make the behavior of the elevator system indeterministic is known before scheduling. The proposed model is based on the trip-based ILP model for static single-car elevator operation problems. A trip of an elevator is a one-directional movement of that elevator, which is labaled upward or downward. In the trip-based ILP model, an elevator trajectory is scheduled according to decision variables which determine allocations of trips to users of an elevator system. That model has such an advantage that the difficulty in solving ILP formulations resulted by that model does not depend on the length of the planning horizon nor the height of the considered building, thus is effective when elevator trajectories are simple. Moreover, that model has many variables relevant to elevators' positions. The proposed model is resulted by adding 3 constraints which are basically based on those variables and make it possible to prevent elevators in a same shaft from interfering. The first constraint simply imposes the first and last floors of an upper trip to be above those of its lower trip. The second constraint imagines the crossing point between upper and lower trips and imposes it ahead of or behind the lower trip according to their directions. The last constraint estimates future positions of elevators and imposes the upper trip to be above floors of passengers on the lower trip. The basic validity of the proposed model is displayed by solving 90 problem instances and examining elevator trajectories generated from them, then comparing objective function values of elevator trajectories on a multi-car elevator system with those on single-car elevator systems.

DOI： 10.1587/transfun.E100.A.385

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Other Link： http://dblp.uni-trier.de/db/journals/ieicet/ieiceta100.html#journals/ieicet/InamotoHK17

Publishing type：Research paper (scientific journal)   Publisher：IEEE  

DOI： 10.1109/ISCIT.2017.8261186

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IOS Press  

In this study, we display preliminary results for harnessing fuzziness of yet-another fuzzy rule-bases. They are based on the pragmatic rule-design (PRD), which has been proposed by the authors. The PRD is novel since a pragmatic rule is not an "IF-THEN" rule nor an artificial neural network, and does not represent a stimulus-response relation. A pragmatic rule is a vector of relative characteristics of effective responses in itself. In the original PRD, the fuzziness in discretizing a system state is too surplus. Restricting such fuzziness may improve the performance of the rule-base, therefore a modification of the original PRD is proposed. Some PRD variants based on that modification are developed and evaluated through their applications to elevator operation problems.

DOI： 10.3233/978-1-61499-828-0-54

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：SPRINGER INTERNATIONAL PUBLISHING AG  

This study conducted a survey to implement educational applications that can share information even in environments where access points cannot be used. In particular, we investigated whether Bluetooth (widely used for many years) or Wi-Fi Direct (developed recently) is more suitable when creating educational applications using an ad hoc network. To survey the influence of hand movements on delay time while operating tablets, we created a paint application that shares a drawing screen across two tablets and conducted an experiment. In addition, to survey the influence of human presence on delay time, we conducted an experiment in which we changed the number of students seated between the two tablets in the classroom. From the results of these experiments, we conclude that Bluetooth is less influenced by hand movements and human presence than Wi-Fi Direct.

DOI： 10.1007/978-3-319-54472-4_33

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Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：The Institute of Electronics, Information and Communication Engineers  

The railway signaling system plays an important role to achieve the safety and the reliability. The income of the railway company is assumed to decrease by the low birthrate and aging. So the railway company is required a reduction of life cycle cost of equipment. In this paper, we propose a new life cycle cost model that considered “the economic loss cost of the passengers who have encountered with the equipment fault” in a life cycle cost model. And we performed various case studies that considered economic loss cost, and confirmed that reduction of the life cycle cost was possible.

DOI： 10.14923/transinfj.2015JDP7085

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electrical and Electronics Engineers Inc.  

The traditional web-based applications operate only when connected to the network. Many realities in a field require a web-based application that is applicable even in case of offline. We have proposed the Automated HTML5 Offline Service (AHOS), presented as the integration of advanced services, developing with HTML5 Application Programming Interfaces (APIs) to provide web-based applications with the ability to work offline. When the AHOS web-based application visits at the web server for the first time, the web server will notify the application the list of files required to be downloaded. Then after being downloaded, the web application can work successfully and continuously even though the network connection from the client to the server is unavailable. Moreover, if the connection to the server is re-connected, any changes that have been made during offline will be automatically uploaded. The present study describes the requirements and implementation stages of AHOS concept for web-based applications. Several current status and challenges of AHOS concept are also explained. The performance analyses of the AHOS concept are performed in a case of web-based maintenance Decision Support System (DSS) for Small and Medium Industries (SMIs). The results of the study are very useful in providing in-depth understanding of the advantages and limitations, and as the future directions in applying this AHOS concept to other web-based applications.

DOI： 10.1109/ICIIBMS.2015.7439480

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：SPRINGER-VERLAG BERLIN  

This paper describes a solution for data synchronization, mobile offline capabilities, and network bandwidth optimization by utilizing a native smart device app as a distributed storage system. The solution aggregates the best practices in business and academic research to achieve a reduction in redundant data transfer and an ability to work offline in smart devices.

DOI： 10.1007/978-3-662-49390-8_6

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：Information Processing Society of Japan  

For the purpose of analyzing the cause of delay in modern digital circuits, efficient diagnosis methods for delay faults need to be developed. This paper presents diagnosis methods for gate delay faults by using a fault dictionary approach. Although a fault dictionary is created by fault simulation and for a specific amount of delay, the proposed method using it can deduce candidate faults successfully even when the amount of delay in a circuit under diagnosis is different from that of the delay assumed during the fault simulation. In this paper, we target diagnosing the presence of single gate delay faults and double gate delay faults. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed methods.

DOI： 10.2197/ipsjtsldm.9.13

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Other Link： http://dblp.uni-trier.de/db/journals/ipsj/ipsj9.html#journals/ipsj/HigamiWTKS16

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

In this paper, we propose a road-map to bridge theoretical and practical approaches in the discipline of the elevator operation problem (EOP). The theoretical approach is to obtain optimal solutions for static EOPs, here "static" means all information on users of the elevator system is known before scheduling. The practical approach is to construct rule-bases for realistic situations. The proposed road-map is comprised of 5 stages: (1) to obtain a formally-optimal solution for a problem instance of a static EOP, (2) to construct a statically-peculiar optimal rule-base from the optimal solution, (3) to construct a dynamically-peculiar optimal rule-base which is effective for the problem instance and functions on a continuous elevator system, (4) to construct a dynamically-narrow rule-base which is effective for a set of problem instances, and (5) to construct a dynamically-wide rule-base which is effective for various sets of problem instances. In computer illustrations, preliminary verification on earlier stages are displayed.

DOI： 10.1109/IIAI-AAI.2016.120

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

BIST based field testing is a promising way to guarantee the functional safety of intelligent and autonomous systems. To improve the fault coverage with less random patterns for BIST, sequentially observing some flip-flops(FFs) during multi-cycle test is useful. In this paper, we propose the methodology for selecting the Fault-Detection-Strengthened FFs in multi-cycle test by evaluating the structure of a circuit. The experimental results of ITC99 benchmarks and a real Electronic Control Unit (ECU) circuit show the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction.

DOI： 10.1109/ATS.2016.40

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

In this paper, we propose a technique to decrease computational times in solving an integer linear programming (ILP) model for the static elevator operation problem (SEOP). The SEOP is a problem to optimally operate elevators on such assumption that all information on passengers who use an elevator system is known beforehand. In planning, there is a symmetry on elevators that exchanging 2 elevators does not affect the value of the objective function, if initial states of those elevators are identical. Such symmetry requires much computational times for problems to be solved, since there are at least 2 optimal solutions which differ only in allocations of elevators and partial solutions for those solutions can not be bound. That symmetry is resolved by giving different roles to elevators, and those roles are assignment pattern numbers (APNs) in the proposed technique. An APN of an elevator is a decimal number which is calculated from a binary vector which represents assignments of passengers to that elevator. The proposed technique deploys such a straightforward fact that all elevators have different APNs, and enfoces an elevator with a smaller index to have a smaller APN than other elevators with larger indexes. The effectiveness of that technique is numerically examined by applying a mathematical solver to ILP equations generated from some problem instances.

DOI： 10.1109/GCCE.2015.7398534

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

It is very difficult, if not impossible, to design hazard free circuits in view of substantial delay uncertainties of gates and interconnects implemented in submicron technologies. In this paper, we propose diagnosis methods for gate delay faults for such circuits. The fault simulation method employed by us uses eight values and calculates logic values as well as earliest transition times and latest transition times. It can deal with hazard signals more accurately than conventional methods. The proposed method uses a fault dictionary to deduce candidate faults which sufficiently explain the output responses of a circuit under diagnosis.

DOI： 10.1109/ISVLSI.2015.67

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2015.67

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CiNii Research

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Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：Reliability Engineering Association of Japan (REAJ)  

With shrinking of LSIs, the diversification of defective mode becomes a critical issue. N-detection tests have been known as an effective way for achieving high defect coverage, however the large number of test pattern counts is the problem. In this paper, we propose metrics(defect detection probability) based on the fault excitation functions to evaluate test patterns for transition faults. We also formulate the method for selecting the test patterns from the N-detection test set based on the defect detection probability as a 0-1 integer linear program. From the experimental results, we show that the set of selected test patterns can detect the larger number of fault models than the given test set with the same number of test patterns.

DOI： 10.11348/reajshinrai.36.8_501

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DOI： 10.11348/reajshinrai.36.8_501

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CiNii Research

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IJNC Editorial Committee  

In this paper, we propose a basic technique to minimize the computational time in executing the infinite-stage dynamic programming (DP) on a GPU. The infinite-stage DP involves computations to probe whether a value function gets sufficiently close to the optimal one. Such computations for probing convergence become obvious when an infinite-stage DP is executed on a GPU, since those computations are not necessary for finite-stage DPs, and hide behind loops for updating state values when a DP is executed on a CPU. The heart of the proposed technique is to suppress those computations for probing by thinning out them. By the proposed technique, differences between state values before and after being updated are periodically transferred to the main memory, then are checked to probe convergence. This intermittent probing makes contrast to ordinary methods in which computations for probing are processed every time. The technique also proposes a formulation to determine optimal periods for probing based on simple statistics given by preliminary experiments. The effectiveness of the proposed technique is examined on two problems; the one is a kind of the animat problem in which an agent moves around in a maze to collect foods, and the other is the mountain-car problem in which a powerless car on a slope struggles to pass over a higher peak. Computational results display that a method with the proposed technique decreases computational times for both problems compared to methods in which computations for probing convergence are processed every time, and the degree of decreasing seems remarkable when the state space is larger.

DOI： 10.15803/ijnc.4.2_321

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Other Link： http://dblp.uni-trier.de/db/journals/ijnc/ijnc4.html#journals/ijnc/InamotoHK14

Language：English   Publishing type：Research paper (scientific journal)   Publisher：The Japan Institute of Electronics Packaging  

In this paper, we introduce a method to measure the resistance of high density post-bond Through Silicon Via (TSV) including serial micro-bumps and bond resistance in Three Dimensional Stacked IC (3D-SIC). The key idea of our technology is to use Electrical Probes embedded in stacked silicon dies. It is a measuring circuit based on Analog Boundary-Scan (IEEE 1149.4). The standard Analog Boundary-Scan structure is modified to realize high measuring accuracy for TSVs in 3D-SIC. The main contribution of the method is to measure the resistance of high pin count (e.g. >10,000) post-bond TSVs accurately. Electrical Probes correspond to the high density of TSV (e.g. < 40 um pitch) and work like Kelvin probe. The measurement accuracy is less than 10 mΩ. We also introduce the preliminary results of small scale measuring experiments and the results of SPICE simulation of large scale measuring circuits.

DOI： 10.5104/jiepeng.7.140

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper presents a diagnosis method for gate delay faults in the presence of clock delay faults. The method deduces candidate faults using a single gate delay fault dictionary and a single clock delay fault dictionary, which contain the information of latest transition time of signals as well as output logic values. To reduce the diagnostic ambiguity we remove those faults from the candidate fault list which provide a contradiction between the circuit responses and responses stored in the dictionary. Since the dictionary is not generated by considering the simultaneous existence of a gate delay fault and a clock delay fault, some heuristic parameters are introduced in order to compensate the difference between the dictionaries and the responses in a circuit under diagnosis.

DOI： 10.1109/ISVLSI.2014.60

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2014.60

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper deals with delay faults on clock lines assuming the launch-on-capture test. In this realistic fault model, the amount of delay at the FF driven by the faulty clock line is such that the scan shift operation can perform correctly even in the presence of a fault, but during the system clock operation, capturing functional value(s) at faulty FF(s), i.e. FF(s) driven by the clock with delay, is delayed and correct value(s) may not be captured. We developed a fault simulator that can handle such faults and using this simulator we investigate the relation between the duration of the delay and the difficulty of detecting clock delay faults in the launch-on-capture test. Next, we propose test generation methods for detecting clock delay faults that affect a single or two FFs. Experimental results for benchmark circuits are given in order to establish the effectiveness of the proposed methods.

DOI： 10.1587/transinf.E96.D.1323

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant of the faulty line but it is also dependent on the signal transition(s) on its adjacent lines. In this paper, we propose an efficient simulation method to simulate small delay faults and we use this simulator to diagnose resistive open faults. The fault simulator developed by us simulates all delay faults for one signal line simultaneously. This information is then used to deduce the candidate faulty lines in two steps. Experimental results for ISCAS'89 benchmark circuits show that by using the method proposed by us the faulty lines can be identified correctly in most cases.

DOI： 10.1109/ATS.2013.23

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2013.23

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

In this paper, we propose a variant of the dynamic programming which is suitable for solving infinite Markov decision processes on GPUs. The primary feature of the proposed method is to not always but intermittently transfer and check values for proving the convergence of the procedure. It is expected for the proposed method to decrease computational times by suppressing surplus transfers and checks of values. This expectation is verified through applications of some dynamic programming programs to a simple animat problem and the mountain-car problem. © 2013 IEEE.

DOI： 10.1109/CANDAR.2013.44

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In this paper, we propose a test generation method for diagnosing transition faults. The proposed method assumes launch on capture test, and it generates test vectors for given fault pairs using a stuck-at ATPG tool so that they can be distinguished. If a given fault pair is indistinguishable, it is identified, and thus the proposed method achieves a complete diagnostic test generation. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at fault, and some additional logic gates are inserted in a CUT during the test generation process. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguished by commercial tools, and also identify indistinguishable fault pairs.

DOI： 10.1587/transinf.E95.D.1093

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Other Link： http://dblp.uni-trier.de/db/journals/ieicet/ieicet95d.html#journals/ieicet/HigamiOYTSA12

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In wavelength-routed WDM networks, blocking probability of lightpath establishments is generally high due to coarse granularity and wavelength continuity constraint. Therefore, blocking of lightpath establishments is one of crucial issues which must be resolved. Multifiber environments reduce blocking probability of lightpath establishments because each link consists of multiple fibers and multifiber links can be viewed as limited-range wavelength conversion. Blocking probability can be further reduced by an appropriate routing and wavelength assignment (RWA) scheme. This paper proposes a dynamic RWA scheme using signaling of backward reservation for wavelength-routed multifiber WDM networks. In the proposed scheme, information on link state is collected by signaling of backward reservation along multiple routes between a sender node and a receiver node whenever a new lightpath-setup request arrives. Then the proposed scheme selects a combination of a route and a wavelength at the receiver node based on the collected information in such a way that it avoids the generation of bottleneck links and the depletion of a specific wavelength. Through simulation experiments, we show that the proposed scheme efficiently reduces blocking probability of lightpath establishments in multifiber WDM networks. © 2012 ACADEMY PUBLISHER.

DOI： 10.4304/jnw.7.9.1441-1448

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

This paper presents diagnosis methods for bridging faults between a clock line and a gate signal line. Scan-based simulation methods are applied while assuming that only scan-based flush tests are used. In view of the fact that initial states play an important role, we consider two possible scenarios: 1) all flip-flops are assumed to be reset table, and 2) flip-flops are not reset table. In order to handle unknown states due to the non-reset table flip-flops, we introduce heuristic techniques. The effectiveness of the proposed methods are evaluated by the experimental results for benchmark circuits. © 2012 IEEE.

DOI： 10.1109/PRDC.2012.15

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Other Link： http://doi.ieeecomputersociety.org/10.1109/PRDC.2012.15

Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

This paper addresses the problem of simultaneous presence of multiple faults consisting of clock delay and gate transitions faults. The conditions of detecting a target multiple fault are converted into those for detecting a single stuck-at fault by adding some logic during the ATPG process. Experimental results show the effectiveness of our method by achieving nearly 100% fault efficiency.

DOI： 10.1109/ETS.2011.27

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ETS.2011.27

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

With shrinking of LSIs, the diversification of defective mode becomes a critical issue. As a result, test patterns for stuck-at faults and transition faults are insufficient to detect such defects. N-detection tests have been known as an effective way for achieving high defect coverage, but the large number of test pattern counts is the problem. In this paper, we propose metrics based on the fault excitation functions and the propagation path function to evaluate test patterns for transition faults. We also propose the method for selecting the test patterns from the N-detection test set. From the experimental results, we show that the set of selected test patterns can detect the larger number of faults than other test set with the same number of test patterns.

DOI： 10.1109/ATS.2011.24

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2011.24

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

Shrinking timing margins for modern high speed digital circuits require a careful reconsideration of faults and fault models. In this paper, we discuss detection of transition faults in the presence of small clock delay faults. We first show that in the presence of a delay fault on a clock line some transition faults may fail to be detected. We propose a test generation method for detecting such faults (simultaneous presence of two faults) which consist of a gate transition fault and a clock delay fault assuming launch-on-capture test environment. The proposed test generation method employs a standard stuck-at ATPG tool. In our test generation methodology, the conditions for detecting a clock delay fault are converted into those for detecting a stuck-at fault, by adding some modeling logic during the ATPG process. Experimental results for benchmark circuits show the effectiveness of the proposed methods.

DOI： 10.1109/ATS.2011.33

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2011.33

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

In this paper, we investigate the effects of delay faults on clock lines under launch-on-capture test strategy. In this fault model we assume that scan-in and scan-out operations, being relatively slow, can perform correctly even in the presence of a fault. However, a flip-flop may fail to capture a value at correct timing during system clock operation, thus requiring the use of launch-on-capture test strategy to detect such a fault. In the paper, we first show simulation results providing a relation between the duration of the delay and difficulty of detecting such faults in the launch-on-capture test. Next, we propose test generation methods to detect such clock delay faults, and show some experimental results to establish the effectiveness of our methods.

DOI： 10.1109/ASPDAC.2011.5722299

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Other Link： http://dl.acm.org/citation.cfm?id=1950967

Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：The Institute of Electronics, Information and Communication Engineers  

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This paper proposes a replica selection and downloading scheme in λ-grid networks. In λ grid networks, in order to distribute loads and achieve high performance computing, a large amount of data is replicated on storage servers as files, and clients download these replicas. To download replicas efficiently, an appropriate replica selection scheme which avoids wavelength contention is required because λ-grid networks employ optical networking. The proposed scheme provides Replica Selection based on Wavelength Availability (RSWA). According to RSWA, a replica is selected based on wavelength availability collected by backward reservation. Furthermore, to suppress blocking probability of download attempts and improve downloading time of replicas, the proposed scheme introduces multiwavelength downloading, which determines the number of wavelengths used for each downloading based on wavelength availability. Through simulation experiments, we show that the proposed scheme can reduce blocking probability of download attempts and improve average downloading time efficiently. © 2010 ACADEMY PUBLISHER.

DOI： 10.4304/jcm.5.9.692-702

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Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.

DOI： 10.1587/transfun.E92.A.3128

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Other Link： http://dblp.uni-trier.de/db/journals/ieicet/ieicet92a.html#journals/ieicet/HigamiSTKT09

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Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publisher：Information and Media Technologies Editorial Board  

Conventional stuck-at fault model is no longer sufficient to deal with the problems of nanometer geometries in modern Large Scale Integrated Circuits (LSIs). Test and diagnosis for transistor defects are required. In this paper we propose a fault diagnosis method for transistor shorts in combinational and full-scan circuits that are described at gale level design. Since it is difficult to describe the precise behavior of faulty transistors, we define two types of transistor short models by focusing on the output values of the corresponding faulty gate. Some of the salient features of the proposed diagnosis method are 1) it uses only gate-level simulation and does not use transistor-level simulation like SPICE, 2) it uses conventional stuck-at fault simulator yet it is able to handle transistor shorts, thus suitable for large circuits, and 3) it is efficient and accurate. We apply our method to ISCAS benchmark circuits to demonstrate the effectiveness of our method.

DOI： 10.11185/imt.4.727

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Conventional stuck-at fault model is no longer sufficient to deal with the problems of nanometer geometries in modern Large Scale Integrated Circuits (LSIs). Test and diagnosis for transistor defects are required. In this paper we propose a fault diagnosis method for transistor shorts in combinational and full-scan circuits that are described at gale level design. Since it is difficult to describe the precise behavior of faulty transistors, we define two types of transistor short models by focusing on the output values of the corresponding faulty gate. Some of the salient features of the proposed diagnosis method are 1) it uses only gate-level simulation and does not use transistor-level simulation like SPICE, 2) it uses conventional stuck-at fault simulator yet it is able to handle transistor shorts, thus suitable for large circuits, and 3) it is efficient and accurate. We apply our method to ISCAS benchmark circuits to demonstrate the effectiveness of our method. © 2009 Information Processing Society of Japan.

DOI： 10.2197/ipsjtsldm.2.250

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In λ-grid networks, data files are stored on file servers as replicas, and those replicas are downloaded in parallel to reduce downloading time. However, parallel downloading raises the blocking probability of lightpath establishments because parallel downloading wastes many wavelength resources. To resolve this problem, we propose a parallel downloading scheme with network coding which encodes data at intermediate nodes. The proposed scheme enables file servers to store many replicas and thus replicas are easily downloaded with low wavelength resources. Through simulation experiments, we show that the proposed scheme improves the blocking probability and the downloading time efficiently. ©2009 IEEE.

DOI： 10.1109/AHICI.2009.5340310

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

Open faults are difficult to test since the voltage at the floating line is unpredicted and depends on the voltage at the adjacent lines. The modeling for open faults with considering adjacent lines has been proposed in [10]. In this work, the 90 nm IC is designed and fabricated to evaluate how the voltage at adjacent lines affect the defective line. The open fault macros with a transmission gate and with an intentional break are included in the IC. The nine lines are placed in parallel in three layers to observe the effect of the coupling capacitance when an open occurs. The benchmark circuits with the open fault macro are also included in the IC. The simulation and experimental results show that the relationship between the floating line and the adjacent lines. The experimental results are also compared with the open fault model that calculate the weighted sum of voltages at the adjacent lines.

DOI： 10.1109/VLSI.Design.2009.60

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Other Link： http://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2009.60

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

With the shrinking process technologies and the use of copper process, open defects on interconnect wires, contacts and vias often cause failure. Development of an efficient fault diagnosis method for open faults is desired. However, the diagnosis method for open faults has not been established yet. In this paper, we propose a novel approach for improving the diagnostic quality of open faults by introducing a threshold function in which the logical value of the line with open defect depends on the weighted logical values of its adjacent lines. By using the threshold function, we can deduce not only a faulty line but also an open defect site at the faulty line. Experimental results show that the proposed method can identify an exact faulty line in most cases with a very small computation cost. The proposed method can also identify the open defect site within 25%-length of the faulty line.

DOI： 10.1109/VLSI.Design.2009.53

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Other Link： http://doi.ieeecomputersociety.org/10.1109/VLSI.Design.2009.53

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper presents a diagnostic test generation method for transition faults. As two consecutive vectors application mechanism, launch on capture test is considered. The proposed algorithm generates test vectors for given fault pairs using a stuck-at ATPG tool so that they are distinguished. If a given fault pair is indistinguishable, it is identified. Therefore the proposed algorithm provides a complete test generation regarding the distinguishability. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at fault, and some additional logic are inserted in a CUT for the test generation. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguished by commercial tools, and also identify all the indistinguishable fault pairs.

DOI： 10.1109/TEST.2009.5355681

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

Under the open fault model with considering the effects of adjacent lines, the open fault excitation is depended on the tests. Therefore, the layout information is needed to generate a test For an open fault. However, it is not easy to extract accurate circuit parameters of a deep sub-micron LSI. We have already proposed an open fault model without using the accurate circuit parameters [6]-[8]. In this paper, we propose a new class of the pair of tests For the open fault called Ordered Pair of Tests (OPT). OPT is generated based on the fault excitation function as a threshold function of the adjacent lines. Also we propose a method for generating OPTs from the given stuck-at fault test set. The proposed method generates OPTs using only information about adjacent lines of the target open fault. Experimental results show that the proposed method can generate the OPTs for the open faults with high fault coverage.

DOI： 10.1109/ATS.2009.39

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2009.39

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

Physical defects that are not covered by stuck-at fault or bridging fault model are increasing in LSI circuits designed and manufactured in modem Deep Sub-Micron (DSM) technologies. Therefore. it is necessary to target non-stuck-at and non-bridging faults. A stuck-open is one such fault model that captures transistor level defects. This paper presents two methods for maximizing stuck-open fault coverage using stuck-at test vectors. In this paper we assume that it test set to detect stuck-at faults is given and we consider two formulations for maximizing stuck-open coverage using the given test set as follows. The first problem is to form a test sequence by using each test vector multiple times, if needed, as long as the stuck-open coverage is increased. In this case the target is to make the resultant test sequence as short as possible under the constraint that the maximum stuck-open coverage is achieved using the given test set. The second problem is to form a test sequence by using each test vector exactly once only. Thus in this case the length of the test sequence is maintained as the number of given test vectors. In both formulations the stuck-at fault coverage does not change. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.

DOI： 10.1093/ietfec/e91-a.12.3506

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In general, we do not know which fault model can explain the cause of the faulty values at the primary outputs in a circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty value on the application of a failing test pattern. In this paper, we propose an effective diagnosis method on multiple fault models, based on only pass/fail information on the applied test patterns. The proposed method deduces both the fault model and the fault location based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing test patterns. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing test patterns. Experimental results show that our method can accurately identify the fault models (stuck-at fault model, AND/OR bridging fault model, dominance bridging fault model, or open fault model) for 90% faulty circuits and that the faulty sites are located within two candidate faults.

DOI： 10.1093/ietisy/e91-d.3.675

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

With the increasing complexity of LSI, Built-In Self Test (BIST) is a promising technique for production testing. We herein propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We refer to fault diagnosis based on the ambiguous test pattern set obtained by the compressed responses of BIST as post-BIST fault diagnosis [1]. In the present paper, we propose an effective method by which to perform post-BIST fault diagnosis for multiple stuck-at faults. The efficiency of the success ratio and the feasibility of diagnosing large circuits are discussed.

DOI： 10.1093/ietisy/e91-d.3.771

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This paper presents methods for detecting transistor short faults using logic level fault simulation and test generation. The paper considers two types of transistor level faults, namely strong shorts and weak shorts, which were introduced in our previous research. These faults are defined based on the values of outputs of faulty gates. The proposed fault simulation and test generation are performed using gate-level tools designed to deal with stuck-at faults, and no transistor-level tools are required. In the test generation process, a circuit is modified by inserting inverters, and a stuck-at test generator is used. The modification of a circuit does not mean a design-for-testability technique, as the modified circuit is used only during the test generation process. Further, generated test patterns are compacted by fault simulation. Also, since the weak short model involves uncertainty in its behavior, we define fault coverage and fault efficiency in three different way, namely, optimistic, pessimistic and probabilistic and assess them. Finally, experimental results for ISCAS benchmark circuits are used to demonstrate the effectiveness of the proposed methods.

DOI： 10.1093/ietisy/e91-d.3.690

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

Defects in the modern LSIs manufactured by the deep-submicron technologies are known to cause complex faulty phenomena. Testing by targeting only stuck-at or bridging faults is no longer sufficient. Yet, increasing defect coverage is even more important. A stuck-open fault model considers transistor level defects, many of which are not covered by a stuck-at fault model. Further, test vectors for stuck-open faults also have the ability to detect the defects modeled by delay faults. This paper presents test generation methods for stuck-open, faults using stuck-at test vectors and stuck-at test generation tools. The resultant test vectors achieve high coverage of stuck open faults while maintaining the original stuck-at fault coverage, thus offering the benefit of potential better defect coverage. We consider two types of test application mechanisms, namely launch on capture test and enhanced scan test. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.

DOI： 10.1109/ATS.2008.39

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2008.39

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

This paper proposes a theory of transistor short faults and their detection in logic test environment. We define transistor short models, and reveal the characteristics of equivalent faults and redundant faults. Also, we present a stuck-at fault simulation method and a test generation method that uses only the gate-level description of the circuits while dealing. with transistor short faults. We present experimental results for ISCAS benchmark circuits to demonstrate the effectiveness of the methodology proposed in this paper.

DOI： 10.1109/VLSID.2007.83

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Other Link： http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.83

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

In order to ensure high quality of DSM circuits, testing for the open defect in the circuits is necessary. However, the modeling and techniques for test generation for open faults have not been established yet. In this paper, we propose a method for generating tests and diagnostic tests based on a new open fault model. Firstly, we show a new open fault model with considering adjacent lines [9]. Under the open fault model, we reveal more about the conditions to excite the open fault. Next we propose a method for generating tests for open faults by using a stuck-at fault test with don't cares. We also propose a method for generating a diagnostic test that can distinguish the pair of open faults. Finally, experimental results show that 1) the proposed method is able to achieve 100% fault coverages for almost all benchmark circuits and 2) the proposed method is able to reduce the number of indistinguished open fault pairs.

DOI： 10.1109/DFT.2007.11

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Other Link： http://doi.ieeecomputersociety.org/10.1109/DFT.2007.11

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

As semiconductor technologies progress, testing of small delay defects are becoming mode important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost.

DOI： 10.1109/DFT.2007.30

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Other Link： http://doi.ieeecomputersociety.org/10.1109/DFT.2007.30

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：SPRINGER  

List-scheduling is a key to achieve high performance for multiprocessor system. The objective is to minimize a processing time of parallel programs. To this end, a lot of scheduling algorithms are proposed. On the other hand, processor utilization may decrease to aim at the shortest processing time. For improvement of processor utilization, there is the deadline method which we have proposed. In this method, we restrict the number of available processors using limitation. In this paper, we show the improvement of processor utilization by proposed method and the validity of the limitation.

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Recently, distributed computing systems are popular among network security researchers. Distributed computing systems have the problem of required programs being analyzed by malicious computers and people. That is to say, in the four senses of a program, the purpose of processing can be analyzed. The easiest solution to this problem is constructed of only trustworthy computers. However, not all computers on the Internet can be considered trustworthy. There are presently no effective security solutions for this problem. We are developing systems to conceal the purpose of processing. In this paper, we prove that the proposed method conceals the purpose of processing. The proposed method is adaptability with the mobile code systems and grid of the distributed computing systems. We are planning on a method of interleaving multiple fragments, and making an effective dummy code and segments.

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Recently there are various requirements for LSI testing, such as test compaction, test compression, low power dissipation or increase of defect coverage. If test sequences contain lots of don't cares (Xs), then their flexibility can be used to meet the above requirements. In this paper, we propose methods for finding as many Xs as possible in test sequences for sequential circuits. Given a fully specified test sequence generated by a sequential ATPG, the proposed methods produce a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence. The methods apply an approach based on fault simulation, and they introduce some heuristics for reducing the simulation effort. Experimental results for ISCAS'89 benchmark circuits show the effectiveness of the proposed methods.

DOI： 10.1093/ietisy/e89-d.11.2748

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DOI： 10.1109/ASPDAC.2006.1594761

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

With the increasing complexity of LSI, Built-In Self Test (BIST) is one of the promising techniques in the production test. From our observation during the manufacturing test, multiple stuck-at faults often exist in the failed chips during the yield ramp-up. Therefore we propose a method for diagnosing multiple stuck-at faults based on the compressed responses from BIST. We call the fault diagnosis based on the compressed responses from BIST the post-BIST fault diagnosis [12, 13]. The efficiency on the success ratio and the feasibility of diagnosing large circuits are discussed. From the experimental results for ISCAS and STARC03 [11] benchmark circuits, it is clear that high success ratios that are about 98% are obtained by the proposed diagnosis method. From the experimental result for the large circuits with 100K gates, we can confirm the feasibility of diagnosing the large circuits within the practical CPU times. We prove the feasibility of diagnosing multiple stuck-at faults on the post-BIST fault diagnosis.

DOI： 10.1109/DFT.2006.24

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We believe that reduction of the testing cost is becoming increasingly important as the size of VLSIs becomes larger. Moreover, as the structure of VLSIs becomes more complicated, test compaction, test compression, and test application time reduction for non-stuck-at faults, such as delay faults, bridging faults, crosstalk faults, and open faults, must be considered. In addition, new methods of fault diagnosis and high-level testing must be developed in order to reduce testing costs or diagnostic costs. In this paper we have surveyed recent research on the reduction of testing cost for logic circuits, including test compaction for combinational circuits and sequential circuits, test compaction under IDDQ testing, and test compression and test application time reduction for scan circuits. © 2005 Wiley Periodicals, Inc.

DOI： 10.1002/scj.20240

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With the scaling of VLSI feature size and increasing complexity of VLSI, it is difficult to determine the cause of failurein a chip. Most of the studies on failure analysis have assumed one fault model, such as single/multiple stuck-at, bridging, or open faults. However, we do not know which fault model can explain a behavior of the defect in the circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty response on the application of a failing test. In this paper, we propose an effective diagnostic method in the presence of unknown fault model, based on only pass/fail information on the applied tests. The proposed method deduces faulty conditions that are able to explain the behavior of the defect in the circuit and locates faulty sites, based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing tests. As a result, we can derive a fault model from the faulty condition. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing tests. Experimental results show that our method can accurately identify the fault models for 93% faulty circuits and that the faulty sites are located within several candidates except for circuits with multiple stuckat faults. © 2005 IEEE.

DOI： 10.1109/ISCAS.2005.1465255

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

With the scaling of VLSI feature size and increasing complexity of VLSI, it is difficult to determine the cause of failure in a chip. Most of the studies on failure analysis have assumed one fault model, such as single/multiple stuck-at, bridging, or open faults. However, we do not know which fault model can explain a behavior of the defect in the circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty response on the application of a failing test. In this paper, we propose an effective diagnostic method in the presence of unknown fault model, based on only pass/fail information on the applied tests. The proposed method deduces faulty conditions that are able to explain the behavior of the defect in the circuit and locates faulty sites, based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing tests. As a result, we can derive a fault model from the faulty condition. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing tests. Experimental results show that our method can accurately identify the fault models for 93% faulty circuits and that the faulty sites are located within several candidates except for circuits with multiple stuck-at faults.

DOI： 10.1109/ISCAS.2005.1465255

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When LSIs that are designed and manufactured for low power dissipation are tested, test vectors that make the power dissipation low should be applied. If test vectors that cause high power dissipation are applied, incorrect test results are obtained or circuits under test are permanently damaged. In this paper, we propose a method to generate test sequences with low power dissipation for sequential circuits. We assume test sequences generated by an ATPG tool are given, and modify them while keeping the original stuck-at fault coverages. The test sequence is modified by inverting the values of primary inputs of every test vector one by one. In order to keep the original fault coverage, fault simulation is conducted whenever one value of primary inputs is inverted. We introduce heuristics that perform fault simulation for a subset of faults during the modification of test vectors. This helps reduce the power dissipation of the modified test sequence. If the fault coverage by the modified test sequence is lower than that by the original test sequence, we generate a new short test sequence and add it to the modified test sequence.

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Other Link： http://dblp.uni-trier.de/db/journals/ieicet/ieicet87d.html#journals/ieicet/HigamiKT04

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

Recently, manufacturing defects including opens in the interconnect layers have been increasing. Therefore, a failure analysis for open faults has become important in manufacturing. Moreover, the failure analysis for open faults under BIST environment is demanded Since the quality of the failure analysis is engaged by the resolution of locating the fault, we propose the method for locating single open fault at a stem, based on only detecting/un-detecting information on tests. Our method deduces candidate faulty stems based on the number of detections for single stuck-at fault at each of fanout branches, by performing single stuck-at fault simulation with both detecting and un-detecting tests. To improve the ability of locating the fault, the method reduces the candidate faulty stems based on the number of detections for multiple stuck-at faults at fanout branches of the candidate faulty stem, by performing multiple stuck-at fault simulation with detecting tests.

DOI： 10.1109/ATS.2004.44

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2004.44

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

We have proposed a method for identifying candidate single stuck-at faults based on the ambiguous test set [9]. In this paper, we propose enhancing methods for diagnosing single/multiple stuck-at faults under BIST environment to reduce the number of candidate faults. The enhancing method uses the number of detections for candidate faults and the first detecting test to diagnose the candidate faults. Moreover, we propose an enhancing method for diagnosing multiple stuck-at faults by using test-pairs.

DOI： 10.1109/ATS.2004.41

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2004.41

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

In this paper, we propose new techniques for finding Xs in test sequences for sequential circuits. Also we show two applications that utilize the obtained test sequences with Xs: reduction of the power during test and test compaction.

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Other Link： http://dblp.uni-trier.de/db/conf/ats/ats2004.html#conf/ats/HigamiKKT04

Language：English   Publishing type：Research paper (scientific journal)  

We have implemented commends of the Autonomous Load Distribution Algorithm(ALD) for general users. ALD is one of inter-node protocol that distributes tasks among computers by negotiation between computers. We had developed and implemented ALD on multi-computer system in the past. But aim of this implementation was just for evaluation. Unfortunately, that was not easy to use for general users. In this paper, we have proposed five commands to use ALD for general users, and implemented these commands. Four of these are barn new commands, and one is same as command that was developed for evaluation in past. User can indicate task distribution in explicit way or in implicit way depending his/her demand. And user can similarly indicate task no-distribution in explicit way or in implicit way. In other words, user can obtain high performance without recognizing existence of ALD. Implementation is based on shell's alias function and trap mechanism. Therefore, this system has higher portability. Alias function is simple, but powerful mechanism. But, it has problem of difference of name and body. This problem is that name indicates incorrect programs if program is changed or overridden. We have solved this problem with shell 's trap mechanism. © 2004, The Institute of Electrical Engineers of Japan. All rights reserved.

DOI： 10.1541/ieejeiss.124.1021

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

In this paper we propose a method to find don't care (X) values in a test sequence for a sequential circuit. Given a fully specified test sequence generated by a sequential ATPG, the proposed method produces a test sequence containing Xs without losing stuck-at fault coverage of the original test sequence.

DOI： 10.1109/ICCD.2003.1240927

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240927

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：KLUWER ACADEMIC PUBLISHERS  

We have proposed "Autonomous Load Distribution Method(ALD)" as one of the load distribution algorithm for multi-computer system. The ALD method requires that node information is reliable in order to distribute load suitably. In this paper, we propose the new ALD method that is appended receiver-initiated function, and apply it on a workstation cluster to compare it with the original method.

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

In this paper we propose two diagnosis methods for crosstalk-induced pulse faults in sequential circuits using crosstalk fault simulation. These methods compare observed responses and simulated values at primary outputs to identify a set of suspected faults that are consistent with the observed responses. The first method is a restart-based method which determines the suspected fault list by using the knowledge about the first and last failures of the test sequence. The advantage of the restart-based method over a method using full simulation is its reduction of the number of simulated faults in a process of diagnosing faults. The second method is a resumption-based method which uses stored state information. The advantage of the resumption-based method over the restart-based method is its reduction of the CPU time for diagnosing the faults. The effectiveness of the proposed methods is evaluated by experiments conducted on ISCAS'89 benchmark circuits. From the experimental results we show that the number of suspected faults obtained by our methods is sufficiently small, and the resumption-based method is substantially faster than the restart-based method.

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In testing of VLSIs designed for low power dissipation, test vectors that avoid excessive power dissipation should be applied. In this paper, we propose a method to modify test vectors for reducing power dissipation in CMOS sequential circuits. Since the power dissipation is proportional to the number of gaies with signal value transitions, we modify test vectors so that they bring less number of gates with signal value transitions. First, we partition a given test sequence into several subsequences, and classify them into (1) subsequences that transfer a circuit to a specific state, and (2) subsequences that activate faults and propagate effects of faults to primary outputs. Next we modify test vectors by changing the value at a primary input one by one. The original stuck-at fault coverage is guaranteed by logic simulation for subsequences in (1), and by fault simulation for subsequences in (2). The proposed method is implemented by C language, and its effectiveness is shown by experimental results for ISCAS'89 benchmark circuits.

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Other Link： http://id.nii.ac.jp/1001/00011636/

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

This paper presents a method to modify test vectors for reducing power dissipation in CMOS sequential circuits. Test vectors are modified by inverting values of primary inputs one by one. With respect to the reduction of power dissipation, we check if the average number of signal transition gates is decreased and if the maximum number of signal transition gates is not increased. Original fault coverage is guaranteed by logic simulation and fault simulation. The effectiveness of the proposed method is shown by experimental results for ISCAS'89 benchmark circuits.

DOI： 10.1109/DELTA.2002.994665

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Other Link： http://doi.ieeecomputersociety.org/10.1109/DELTA.2002.994665

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

For recent VLSIs designed for low power, reduction of power dissipation during test is one of the most important problems. This paper presents a method to reduce power dissipation during test for sequential circuits. The goal is to obtain test vectors for sequential circuits that achieve low power dissipation. In our method, test vectors generated by A TPG are given and they are improved to reduce power dissipation without losing the original stuck-at fault coverage. Due to the correlation between power dissipation and the number of transition gates, the number of transition gates is evaluated for each test vector during modification of test vectors. In order to keep the original fault coverage, logic simulation and fault simulation are performed, every time a test vector is modified. The effectiveness of our method is shown by experimental results for ISCAS 89 benchmark circuits.

DOI： 10.1109/ATS.2002.1181732

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In this paper, we propose a test generation method for double stuck-at faults. The proposed method consists of main three parts,
1) Fault simulation with the application of test patterns generated for single stuck-at faults
2) Identification of undetectable faults
3) Test generation using a test generator for single stuck-at faults.
The effectiveness of the proposed method is shown by experimental results for ISCAS'85 benchmark circuits.

DOI： 10.1109/ATS.2001.990261

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2001.990261

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

This paper describes two methods of diagnosing crosstalk-induced pulse faults in sequential circuits using crosstalk fault simulation. These methods compare with observed responses and simulated values at primary outputs to identify a set of suspected faults that are consistent with the observed responses. In these methods, if the simulated values agree with the observed responses, then the simulated fault is added to a set of suspected faults, otherwise the simulated fault is removed from the set of suspected faults. The diagnosis methods repeat the above process for each time-frame to identify the suspected faults. The first method is a basic method which determines the suspected fault list by using the knowledge about the first and last failures of the test sequence. The second method uses state information and focuses on reducing the CPU time for diagnosing the faults. The CPU time is reduced by using stored state information to calculate the primary output values at the present time frame. Experimental results for ISCAS'89 benchmark circuits show that the number of suspected faults obtained by our methods is sufficiently small, and the second method is substantially faster than the first method.

DOI： 10.1109/ATS.2001.990260

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2001.990260

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

In this paper, we propose a static test compaction method for sequential circuits with reset states under single stuck-at fault assumption. The proposed method first finds unremovable vectors by fault-dropping fault simulation or by non-fault-dropping fault simulation. Next, a subset of test vectors other than unremovable vectors are replaced with a reset signal. Detection of faults detected by an original test sequence is guaranteed by logic simulation and fault simulation for test subsequences. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method.

DOI： 10.1109/ATS.2000.893620

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2000.893620

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：ACM  

This paper surveys recent research related to IDDQ testing, particularly focuses on fault models and test generation methods. (1) The paper pro videsa taxonomy of fault models that have been studied in literature, and classifies these models into a small set of faults. (2) The paper describes efficient test generation methods and fault simulation methods. Test compaction methods, including reduction of the total number of test vectors and selection of IDDQ measurement vectors, are also described. © 2000 IEEE.

DOI： 10.1145/368434.368773

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Other Link： http://dblp.uni-trier.de/db/conf/aspdac/aspdac2000.html#conf/aspdac/HigamiTSK00

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Scripta Technica Inc  

This paper presents a static test compaction method for IDDQ testing of sequential circuits. Test compaction reduces test application time and tester memory and consequently reduces testing cost. Particularly for IDDQ testing, measurement of IDDQ is time-consuming, and thus test compaction is a very important issue. In the proposed method, test subsequences are removed and replaced with shorter subsequences by considering state transition of a circuit under test, so that original fault coverage is guaranteed. The effectiveness of the proposed method is demonstrated by experimental results for ISCAS'89 benchmark circuits.

DOI： 10.1002/1520-684X(200010)31:11<41::AID-SCJ5>3.0.CO;2-F

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In order to reduce IDDQ testing time, it is important to reduce the number of IDDQ measurement vectors, because IDDQ measurement is a time-consuming process. For obtaining minimum number of IDDQ measurement vectors for sequential circuits, fault simulation needs to be performed without fault-dropping, thus requiring very high simulation time. In this paper we propose algorithms to select small number of IDDQ measurement vectors. The proposed algorithms can concurrently simulate multiple faults and use heuristics for selection of IDDQ measurement vectors to reduce simulation time. Experimental results are presented to demonstrate the effectiveness of the proposed method.

DOI： 10.1023/A:1008360430959

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Language：Japanese   Publishing type：Research paper (scientific journal)   Publisher：The Institute of Electronics, Information and Communication Engineers  

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

In IDDQ testing, long testing time is one of the significant problems, because IDDQ measurement is a time consuming process. In order to reduce the testing time, it is important to reduce the number of IDDQ observation vectors rather than the number of total test rectors. In this paper we propose efficient techniques to select small number of IDDQ observation vectors. The proposed techniques are use of a concept of essential vectors and concurrent fault simulation. Experimental results for ISCAS '89 benchmark circuits show that the proposed technique reduces the number of IDDQ observation vectors with short computational time.

DOI： 10.1109/ICVD.1999.745127

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ICVD.1999.745127

Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

DOI： 10.1109/ATS.1999.810742

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.1999.810742

Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG  

This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal slates. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By rising the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE COMPUTER SOC  

One of the major unsolved and ignored but significant problem is reduction of long testing time for IDDQ testing of CMOS circuits. Since IDDQ must be observed after dynamic current disappears, testing time Is much longer than logic testing. This paper presents a method to reduce the observation time for IDDQ testing The proposed method is a static method which focuses on selection of vectors to be observed instead of removing vectors. Experimental results are presented to demonstrate the effectiveness of the proposed method.

DOI： 10.1109/ATS.1998.741631

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.1998.741631

Publisher：IEEE Computer Society  

DOI： 10.1109/EDTC.1997.582439

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Other Link： http://doi.ieeecomputersociety.org/10.1109/EDTC.1997.582439

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：I E E E, COMPUTER SOC PRESS  

DOI： 10.1109/ATS.1996.555143

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.1996.555143

Language：English   Publishing type：Research paper (scientific journal)   Publisher：KLUWER ACADEMIC PUBL  

This paper presents a partial scan algorithm, called FARES (Partial scan Algorithm based on REduced Scan shift), for designing partial scan circuits. FARES is based on the reduced scan shift that has been previously proposed for generating short test sequences for full scan circuits. In the reduced scan shift method, one determines which FFs must be controlled and observed for each test vector. According to the results of similar analysis, FARES selects these FFs that must be controlled or observed for a large number of test vectors, as scanned FFs. Short test sequences are generated by reducing scan shift operations using a static test compaction method. To minimize the loss of fault coverage, the order of test vectors is so determined that the unscanned FFs are in the state required by the next test vector. If there are any faults undetected yet by a test sequence derived from the test vectors, then FARES uses a sequential circuit test generator to detect the faults. Experimental results for ISCAS'89 benchmark circuits are given to demonstrate the effectiveness of FARES.

DOI： 10.1007/BF00993319

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DOI： 10.1109/ATS.1995.485333

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.1995.485333

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：I E E E  

DOI： 10.1109/TEST.1994.528007

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Language：Japanese   Publishing type：Research paper, summary (national, other academic conference)   Publisher：一般社団法人エレクトロニクス実装学会  

次世代のIoTエッジデバイス向けのメモリベース論理再構成デバイスMRLD(Memory-based Reconfigurable Logic Device）では，IoTシステムとしての高信頼性を保証するために，運用中に劣化状態を早期に検知・報告する劣化障害予告技術が求められる．本研究では，MRLDデバイスの構成要素であるLUTでの経年劣化による遅延を計測するために，MRLDデバイスの構造に適した遅延計測論理回路用リングオシレータを設計し，その実装方法を提案する。さらに，論理シュミレーションによって提案法の有効性を評価する。

DOI： 10.11486/ejisso.34.0_4c1-02

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The external grid is one of grid computing systems. It is composed of numerous computers connected to the Internet. Although the external grid realizes high performance computing, it is necessary to guarantee the robustness against malicious behaviors of the computers. In the previous literature, a technique to protect program codes against such behaviors has been proposed; however, only one type of malicious behavior is considered to evaluate the effectiveness of the technique in the literature. In reality, malicious behaviors vary according to the purpose of malicious groups. The goal of the research in this paper is to guarantee the safety of the external grid in a quantitative way. In order to achieve the goal, we evaluate the effectiveness of concealing processes against several types of malicious behaviors.

DOI： 10.1007/978-3-319-48429-7_11

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Resistive Open Faults (RoF) are known to be major sources of small delays in Deep Sub-Micron devices. Excessive IR drop during test results in delay variation that would cause incorrect diagnosis for small delay faults such as RoFs. We believe that the patterns with low IR drop can help avoid incorrect diagnosis. Therefore, we propose a test pattern selection method for RoF diagnosis under the constraint of low IR drop. Our method first selects the patterns for target faults whose longest sensitized path have high IR drop from a pre-generated test set, and then it conducts x-identification and x-filling on the risky pattern set to generate safety patterns with low IR drop for the target faults. Simulated Annealing algorithm is introduced for exploring the best x-filling. Experimental results show the effectiveness of our selection.

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Since the 3D integrated circuit (3D-IC) consists of several dies that are connected by the huge number of through-silicon vias (TSVs), the yield of a 3D-IC makes an impact on the chip cost. Therefore, development of testing technology for 3D-IC becomes essential for reducing the manufacturing cost of 3D-IC. In this chapter, we describe the testing technologies for 3D-IC. In Sect. 8.1, we marshal the issues that must be handled in the 3D-IC testing. From Sects. 8.2 to 8.4, we introduce the outlining of the proposed 3D-IC testing technologies in so far. From Sects. 8.5 to 8.7, we provide the 3D-IC testing technologies that are proposed by our research group in Japan.

DOI： 10.1007/978-3-319-18675-7_8

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This paper describes a lightweight image storage system, called Sushi, which has been designed for high traffic mobile and Web applications. The system aggregates the best practices in business and academic researches to achieve simplicity while providing high performance, availability, and scalability. The key design feature of the system is its use of an underlying nonblocking architecturewith current software standards.

DOI： 10.1007/978-3-319-15147-2_11

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In this study, some preliminary results on optimality of elevator operations by a zoning technique are displayed. This study is motivated by the desire of decreasing computational times to obtain optimal elevator operations for static elevator operation problems (SEOPs), in which all information on users of the elevator system and the initial floors of elevators are known beforehand. If optimal results are obtainable even if a zoning technique is deployed, then we can expect that deploying the technique limits search spaces of problems and yields optimal results in shorter computational times. The study is conducted by comparing an optimal elevator operation and a near-optimal elevator operation for some problem instances of the SEOP. The former operation is obtained by solving an integer programming problem (IP) deduced from a problem instance. The way of obtaining the latter operation is same to the former except that the handled IP is modified to involve equations which represent the zoning technique. Ten problem instances are generated for each combination of the traffic pattern and the number of system users, and finally 60 problem instances are considered in total.

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Language：English   Publisher：IEEE  

In this paper, we propose an integer linear programming (ILP) model for static elevator operation problems. The proposed model is based on hall- and car-calls which correspond to pickup and delivery requests in pickup-and-delivery problems (PDPs), thus is similar to ILP models for PDPs. The primary difference between those models and the proposed model is the prevention of the reverse run, which means that an elevator with a passenger is moved to the direction opposite to that of the passenger. In computer illustrations, the proposed model is roughly investigated by being compared with a trip-based ILP model which has been proposed by the authors.

DOI： 10.1109/SCIS-ISIS.2014.7044775

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Language：English   Publisher：IEEE  

In this paper, we propose a technique to decrease computational times for solving static elevator operation problems which are formalized as trip-based integer linear programming models. The technique is comprised of two parts: (i) to give equations which constrain the search space on the assumption that the maximum waiting time over passengers of an optimal solution is known, and (ii) to estimate such time as longest round-trip times. Computational results indicate that the technique can basically decrease computational times without degrading objective function values when maximum waiting times are less than estimated values and the number of equipped elevators is 1.

DOI： 10.1109/GCCE.2014.7031178

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Language：English   Publisher：IEEE  

In this paper, we propose a new method that can measure the resistance of high density post-bond TSVs including serial micro-bumps and bond resistance. The key idea of the proposed technology is to use Electrical Probe embedded in the stacked silicon dies. It is a measuring circuit based on Analog Boundary-Scan (IEEE1149.4). We modify the standard Analog Boundary-Scan structure to realize the high measuring accuracy for TSVs in 3D-SIC. The main contribution of the method is to measure the resistance of high pin count (e.g. &gt; 10,000) post-bond TSVs accurately. Electrical Probes correspond to the high density of TSV (e.g. &lt; 40 um pitch) and work like as Kelvin probe. The measurement accuracy is less than 10 m Omega. We also introduce the preliminary results of small scale measuring experiments and the results of SPICE simulation of large scale measuring circuits.

DOI： 10.1109/ICEP.2014.6826673

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電子機器の小型化・高機能化に伴って,実装ボード上のIC間の相互接続をテストするためのバウンダリスキャンテストが必要不可欠となりつつある.本論文では,これまでほとんど論じられることがなかった,バウンダリスキャンテスト実行中のIC内部で起こっている回路の振舞いを分析し,テスト上の課題について言及する.更に,その課題に対する対策を述べる.

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When a resistive open fault occurs, signal delay at the faulty wire may degrade circuit performance However, a resistive open fault is difficult to test since some test patterns do not cause logical errors at the faulty circuit even if the pattern provides a transition at the faulty wire In this study, we investigate the output char-acteristic of wires with a open fault using electromagnetic simulator for detecting resistive open faults We apply simulation for several layouts to estimate the delay caused by the defect size, the length of adjacent lines, and different combinations of input signals at the adjacent lines The simulated results show the effects of these parameters on the signal delay.

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In this paper, we propose a technique for a trip-based integer programming model for elevator operations to decrease computational times in solving problems for multiple elevators. The technique is inspired by the speculation on ideal trajectories of elevators, where the interval of arriving floors is equal to each elevator. Such trajectories are regarded as oscillating waves. It is expected that limiting movements of elevators to resemble such waves may decrease computational times without degradation on the objective value. This expectation is numerically examined by obtaining optimal trajectories of some problem instances. © 2013 IEEE.

DOI： 10.1109/GCCE.2013.6664807

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Language：Japanese   Publisher：電子情報通信学会  

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Language：Japanese   Publishing type：Rapid communication, short report, research note, etc. (scientific journal)   Publisher：一般社団法人電子情報通信学会  

We try to empirically study signal integrity-defects. In this study, we analyze the resistive open fault that causes the signal integrity-defect by using the three-dimensional (3-D) electromagnetic software and the TEG with the resistive open faults. We propose a method for generating the test patterns for the resistive open faults under the launch-off-capture (LOC) test. We also propose a method for diagnosing the resistive open faults by using the diagnostic delay fault simulation with considering the affects of the adjacent lines.

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The miniaturization of electronic products is causing printed circuit boards to progress in the direction of higher density, using, for example, BGA (Ball Grid Array) devices. In this situation, Boundary-scan Test technology is increasingly more important, since it is the best way to detect manufacturing defects easily on the dense boards. This paper describes a side-effect caused by an internal disruption within an IC during the Boundary-Scan test, and also describes the root-cause and the measures for it on the basis of our experience.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

The miniaturization of electronic products is causing printed circuit boards to progress in the direction of higher density, using, for example, BGA (Ball Grid Array) devices. In this situation, Boundary-scan Test technology is increasingly more important, since it is the best way to detect manufacturing defects easily on the dense boards. This paper describes a side-effect caused by an internal disruption within an IC during the Boundary-Scan test, and also describes the root-cause and the measures for it on the basis of our experience.

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Language：English   Publisher：WYDAWNICTWO SIGMA-N O T SP Z O O  

Technology of concealing purpose of program is needed for profitable uses of an external grid. We propose dummy code insertion technique for concealment technology. We have implemented one kind of technique of dummy code insertion on trail. Moreover we evaluate strength of concealment against malicious inspection. We explain the detail of evaluation of dummy code insertion technique in this paper.

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Language：English   Publisher：Institute of Electronics, Information and Communication, Engineers, IEICE  

In this paper, we propose a test generation method for diagnosing transition faults. The proposed method assumes launch on capture test, and it generates test vectors for given fault pairs using a stuck-at ATPG tool so thst they can be distinguished. If a given fault pair is in-distinguishable, it is identified, and thus the proposed method achieves a complete diagnostic test generation. The conditions for distinguishing a fault pair are carefully considered, and they are transformed into the conditions of the detection of a stuck-at-fault, and some additional logic gates are inserted in a CUT during the test generation process. Experimental results show that the proposed method can generation process. Experimental results show that the proposed method can generate test vectors for distinguishing the fault pairs that are not distinguised by commercial tools, and also identify indistinguishable fault pairs. Copyright © 2012 The Institute of Electronics, Information and Communication Engineers.

DOI： 10.1587/transinf.E95.D.1093

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Language：Japanese   Publisher：一般社団法人電子情報通信学会  

DOI： 10.1587/ieiceissjournal.17.3_13

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This paper proposes a dynamic routing and wavelength assignment (RWA) scheme in multifiber WDM networks with sparse wavelength conversion. In multifiber environments, each link consists of multiple fibers. Thus, lightpaths with the same wavelength can be established in the same link as long as they use different fibers. In WDM networks with sparse wavelength conversion, only a subset of the network nodes has wavelength conversion capability which can convert one wavelength to another. In order to efficiently utilize these environments, an appropriate RWA scheme is necessary. The proposed scheme provides RWA for multifiber WDM networks with sparse wavelength conversion. In the proposed scheme, a route and wavelengths are selected for each lightpath based on wavelength availability and location of nodes with wavelength conversion capability. Through simulation experiments, we show that the proposed scheme reduces the blocking probability of lightpath establishments efficiently. © 2012 IEEE.

DOI： 10.1109/ICTC.2012.6387201

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With shrinking of LSIs, the diversification of defective mode due to defects becomes a critical issue. Therefore, test patterns for stuck-at faults and transition faults are insufficient to detect such defects. In this paper, we propose metrics based on the fault excitation functions and the propagation path function to evaluate test patterns for transition faults. We also propose the method for selecting the test patterns from the n-detection test set. From the experimental results, we show that the set of selected test patterns can detect more fault models under the less number of test patterns.

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This paper proposes a wavelength selection scheme based on wavelength availability in multi-fiber WDM networks. In multi-fiber WDM networks, each link consists of multiple optical fibers. The proposed scheme collects information on wavelength availability on fibers along a route between a source node and a destination node. Then the proposed scheme selects a wavelength based on the collected information in such a way that it makes wavelength usage in links smooth. By doing so, the generation of bottleneck links is suppressed. Through simulation experiments, we show that the proposed scheme efficiently improves blocking probability in multi-fiber WDM networks. © 2011 IEEE.

DOI： 10.1109/ICMT.2011.6002117

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OLSR is a proactive routing protocol for mobile ad hoc networks (MANETs). OLSR uses a concept of MPR selection mechanism to reduce broadcast packets during a flooding process. MPR nodes use more energy than nonMPR nodes. Thus they easily run out their energy since mobile nodes in MANETs are powered by battery with limited energy. This paper proposes a residual energy-based OLSR protocol named REOLSR2. The REOLSR2 selects MPR nodes based on not only reachability and degree but also residual energy of 1-hop neighbors. The aim is to avoid selecting MPR nodes which has small residual energy and concentrating energy consumption in specific nodes. Simulation results show that the proposed scheme reduces energy consumption and enhances network throughput efficiently. © 2011 IEEE.

DOI： 10.1109/ICMT.2011.6002054

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Language：English   Publisher：一般社団法人電子情報通信学会  

This paper proposes a dynamic routing and wavelength assignment (RWA) scheme using signaling of backward reservation in multifiber WDM networks. In the proposed scheme, information on link state is collected by signaling of backward reservation along multiple routes between a sender node and a receiver node whenever a new lightpath-setup request arrives. Then the proposed scheme selects a combination of a route and a wavelength at the receiver node based on the collected information in such a way that it makes wavelength usage in the routes smooth. Through simulation experiments, we show that the proposed scheme efficiently improves blocking probability of lightpath establishments in multifiber WDM optical networks. © 2011 IEEE.

DOI： 10.1109/ICTC.2011.6082635

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This paper proposes a dynamic routing and wavelength assignment (RWA) scheme using signaling of backward reservation in multifiber WDM networks. In the proposed scheme, information on link state is collected by signaling of backward reservation along multiple routes between a sender node and a receiver node whenever a new lightpath-setup request arrives. Then the proposed scheme selects a combination of a route and a wavelength at the receiver node based on the collected information in such a way that it makes wavelength usage in the routes smooth. Through simulation experiments, we show that the proposed scheme efficiently improves blocking probability of lightpath establishments in multifiber WDM optical networks. © 2011 IEEE.

DOI： 10.1109/ICTC.2011.6082635

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Auxons is a non-relational column-based distributed storage system for managing a very large amounts of semi-structured data to scale out among thousands of commodity servers, while providing high availability and high performance. In many ways Auxons is simple and flexible compare to RDBMS: to leave a complex, often-unused RDBMS features, schema free, elastic table evolving, and no pre-defined data formats (everything is string). Adding, editing and retrieving the data through a simple set of API calls. In practice this type non-relational storage systems are used for cloud services, though they typically do not support ACID transaction and with a goal of massive scaling. In this paper, we describe the design and implementation of Auxons as our solution of middleware for cloud services.

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Language：Japanese   Publisher：一般社団法人電子情報通信学会  

This paper proposes a replica selection and transmission scheme in optical gird networks. In optical grid networks, in order to distribute loads, a large amount of data is replicated on storage servers as files, and clients download those replicas. The proposed scheme provides replica selection based on wavelength availability which is collected by signaling of backward reservation. Furthermore, the proposed scheme introduces a multi-wavelength transmission which determines the number of wavelengths used for each replica transmission based on wavelength availability. Through simulation experiments, we show that the proposed scheme can improve the blocking probability of file transmission and the average transmission time efficiently.

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Language：Japanese   Publisher：一般社団法人電子情報通信学会  

Countermeasures against an open fault in LSI testing become more important with advancement of LSI process technology. However, a practicable modeling of the open fault has not been performed yet. So, we have fabricated TEG(Test Element Group)chips into which open defects is intentionally built, and then we research on modeling the open fault based on the measurement data of the TEG chips. In this paper, modeling of the open fault is considered. A technique to calculate the influence of adjacent lines on the faulty line based on digital measurement data of the TEG chips using RCGA(Real-Coded Genetic Algorithm)is proposed. The proposed model based on the digital measurement using RCGA can mostly simulate the logical value of the line with open fault, and shows high quality without considering the interconnect structure. Moreover, we attempt to simplify the model by averaging the influence of adjacent lines, and the simplification shows effectiveness.

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Language：Japanese   Publisher：一般社団法人電子情報通信学会  

In order to solve the problem of signal integrity, we propose an extended delay fault model for modeling a resistive open fault. We use the three-dimensional electromagnetic software to analyze the behavior of a line with the resistive open. Under the extended delay fault model proposed in this paper, the size of the additional delay is depended on the signal transitions at the adjacent lines that are assigned by the test-pair. Under the launch on capture(LOC)test, we propose a method for generating the test-pairs for the resistive open faults by using the transition fault tests with don&#039;t cares. We demonstrated the experimental results to show that the proposed method is able to generate the test-pair for resistive open faults that cannot be detected by the given test-pairs for the transition faults.

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Language：Japanese   Publisher：一般社団法人電子情報通信学会  

This paper proposes a wavelength scheduling scheme based on traffic characteristics in optical grid networks. There are two types of traffic in optical grid networks. One is streaming traffic such as that in real time collaborative visualization sessions, and the other is elastic traffic which consists of data sets (files or parts of files). Generally, to reserve wavelengths, immediate reservations and advance reservations are used for streaming traffic and elastic traffic, respectively. When those reservations are used concurrently, immediate reservations are often blocked because advance reservations have priority use of wavelength resources. The proposed scheme controls advance reservations based on wavelength usage and availability of immediate reservations. Through simulation experiments, we show that the proposed scheme can reduce the blocking probability of immediate reservations and improve fairness of blocking probabilities of immediate and advance reservations.

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It is believed that resistive open faults can cause small delay defects at wires, contacts, and/or vias of a circuit. However, it remains to be elucidated whether any methods could diagnose resistive open faults. We propose a method for diagnosing resistive open faults by using a diagnostic delay fault simulation with the minimum detectable delay fault size. We also introduce a fault excitation function for the resistive open fault to improve the accuracy of the diagnostic result. The fault excitation function for the resistive open fault can determine a size of an additional delay at a faulty line with considering the effect of the adjacent lines. We demonstrated that the proposed method is capable of identifying fault locations for the resistive open fault with a small computation cost. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665061

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Faulty effects caused by a hard open defect at an interconnect line in a 90nm CMOS IC are analyzed by device simulation in this paper. The simulation results reveal us that output voltage of the floating interconnect line is obtained as linear sum of effects from logic signals of the adjacent interconnect lines and the defective one. Also, an estimation model of voltage at the floating interconnect line is proposed. Feasibility of the estimation is examined in this paper. The result shows us that the voltage can be estimated within error of about 0.03V. ©2010 IEEE.

DOI： 10.1109/ISCIT.2010.5665062

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Language：Japanese   Publisher：一般社団法人電子情報通信学会  

This paper proposes a replica selection scheme with backward reservation in λ-grid networks. In λ-grid networks, in order to distribute loads and achieve high performance computing, a large amount of data is replicated on storage servers in multiple sites as files, and clients can download files from one of those sites. To download those files efficiently, a replica selection scheme which avoids wavelength contention is needed in λ-grid networks because λ-grid networks employ optical networking. The proposed scheme collects information of multiple sites with signaling and selects a replica based on the information. Through simulation experiments, we show that the proposed scheme can decrease the probability of wavelength contention efficiently.

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