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File： ITC-Asia2024_cameraready0627.pdf

DOI： 10.1109/itc-asia62534.2024.10661324

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

File： ITC-CSCC_2024_CameraReady_v2.pdf

DOI： 10.1109/itc-cscc62988.2024.10628398

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Language：Japanese   Publishing type：Research paper (scientific journal)  

DOI： 10.11486/ejisso.28.0_231

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With the aggressive scaling in the feature size of transistors, single-event triple-node-upsets (TNUs) induced by charge sharing in CMOS circuits have become a significant reliability problem. In this paper, based on N-type stacked transistors, a TNU self-recovery latch called LORD-TNU is proposed. Utilizing the stacked transistors to reduce the count of sensitive nodes in the latch. In addition, we use three modules to protect each other. In the event of a soft error in one module, the remaining modules can restore the corrupted module. This design not only saves delay overhead but also minimizes area overhead. Simulation results show that compared with the four typical TNU hardened latches, the proposed LORD-TNU latch reduces area overhead by 49.76%, power consumption by 56.07%, delay by 40.17%, and the power-delay-product (PDP) by 72.56% on average, respectively. Moreover, the robustness of our LORD-TNU latch is confirmed by comprehensive PVT (Process, Voltage, Temperature) and Monte Carlo simulations, demonstrating its stability across a range of process corners, supply voltage, and temperature variations.

DOI： 10.1109/TDMR.2024.3386954

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Language：Japanese   Publisher：The Japan Institute of Electronics Packaging  

DOI： 10.5104/jiep.27.169

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File： P15_France_SAS_JTAG_Security for DFT2023_camera ready_final_final - コピー.pdf

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File： P2_e107-d_1_60 (2).pdf

DOI： 10.1587/transinf.2023EDP7101

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DOI： 10.1145/3610295

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Test point insertion is an effective approach for improving fault diagnosis ability as well as testability. This paper presents a test points, as observation points, insertion for improving fault diagnosis ability. In order to find suitable observation points, scores are calculated on signal lines for each fault pair that is not distinguished by the given test set. After selecting observation points, the proposed method partitions primary outputs and the inserted observation points into groups such that the output responses in the same group are compacted by XOR operation. The partition method allows to reduce the number of values to be observed without decreasing the diagnosis ability. The effectiveness of the proposed method is validated by experiments on benchmark circuits.

DOI： 10.1109/ITC-CSCC58803.2023.10212844

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Authorship：Lead author,　Corresponding author   Language：English   Publishing type：Research paper (scientific journal)   Publisher：Association for Computing Machinery (ACM)  

Under the functional safety standard ISO26262, automotive systems require testing in the field, such as the power-on self-test (POST). Unlike the production test, the POST requires reducing the test application time to meet the indispensable test quality (e.g., >90% of latent fault metric) of ISO26262. This article proposes a test point insertion technique for multi-cycle power-on self-test to reduce the test application time under the indispensable test quality. The main difference to the existing test point insertion techniques is to solve the fault masking problem and the fault detection degradation problem under the multi-cycle test. We also present the method to identify a user-specified amount of test points that could achieve the most scan-in pattern reduction for attaining a target test coverage. The experimental results on ISCAS89 and ITC99 benchmarks show 24.4X pattern reduction on average to achieve 90% stuck-at fault coverage confirming the effectiveness of the proposed method.

File： P4_ACM3563552.pdf

DOI： 10.1145/3563552

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Authorship：Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)  

Identifying optimal test points to maximize fault coverage is crucial for improving field tests of large-scale integrated circuits (LSIs). In this paper, we introduce Deep-TPs-Explorer, a method that utilizes deep graph-convolutional neural networks (GCNs) to identify a more effective set of test points, thereby enhancing the random testability of logic circuits. For efficient training of the GCN, we employ the Advantage Actor-Critic (A2C) reinforcement learning algorithm. The effectiveness of our proposed method is validated using the ISCAS89 and ITC99 benchmark circuits.

File： P17_ITCCSCC2023_submission_final.pdf

DOI： 10.1109/ITC-CSCC58803.2023.10212888

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Other Link： https://dblp.uni-trier.de/rec/conf/apnoms/2023

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Authorship：Lead author,　Corresponding author   Language：Japanese   Publisher：Japan Institute of Electronics Packaging  

DOI： 10.5104/jiep.24.668

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Use of a fault dictionary is an effective and efficient method for deducing candidate faults during fault diagnosis process. It contains output responses for every test pattern and every target fault, and therefore the size of the fault dictionary for large LSIs tends to be very large. This paper proposes methods for compacting a fault dictionary without loss of diagnosis ability. We assume that output responses are compacted by an XOR tree compactor, and we investigate how we make the groups of primary outputs for which values are compacted by XOR operation. The methods introduce measures that are based on the number of distinguished fault pairs and the number of detecting test patterns. The effectiveness of the proposed methods is demonstrated by conducting experiments on a number of benchmark circuits.

DOI： 10.1109/itc-cscc52171.2021.9501474

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Authorship：Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

MRLD (TM) is a new type of reconfigurable device constructed by general SRAM array (multiple-LUTs) which has the advantages including small delay, low power and low production cost. It is therefore a promising alternative device for Artificial Intelligence applications such as neural networks (NNs). However, implementing a traditional NNs with fully connected NNs is a hard task due to the special interconnection structure of SRAM array (the multiple look-up tables: MLUTs) in MRLD. In this paper, we suggest a LUT-based neuron model to realize neuron functions by writing truth table in SRAM array, and propose a novel neural network structure named MNN (MRLD-based Neural Network) to adapt the special connection structure of MLUTs for implementing a NNs application into MRLD. To evaluate the effectiveness of MNN, we perform the experiments by training MNN with the MNIST dataset. The experimental results show that the MNN can get almost the same accuracy and loss for MNIST data recognition compared to a fully connected NN.

DOI： 10.1109/itc-cscc52171.2021.9501454

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Authorship：Corresponding author   Language：English   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electronics, Information and Communications Engineers (IEICE)  

Multi-cycle Test looks promising a way to reduce the test application time of POST (Power-on Self-Test) for achieving a targeted high fault coverage specified by ISO26262 for testing automotive devices. In this paper, we first analyze the mechanism of Stuck-at Fault Detection Degradation problem in multi-cycle test. Based on the result of our analysis we propose a novel solution named FF-Control Point Insertion technique (FF-CPI) to achieve the reduction of scan-in patterns by multi-cycle test. The FF-CPI technique modifies the captured values of scan Flip-Flops (FFs) during capture operation by directly reversing the value of partial FFs or loading random vectors. The FF-CPI technique enhances the number of detectable stuck-at faults under the capture patterns. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of FF-CPI technique in scan-in pattern reduction for POST.

DOI： 10.1587/transinf.2019EDP7235

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Authorship：Corresponding author   Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

MRLD is a new type of reconfigurable device constructed by general SRAMs array that is promising to use for the next-generation IoT edge devices. During the operation of the MRLD, aging-induced failures may occur without any previous notice, which greatly affects the reliability of the entire IoT systems. In this paper, we propose a method for early detecting and reporting the effect of the aging in MRLD. The method configures a new designed ring oscillator circuit into the MRLD for monitoring its internal delay variations. Simulation results confirmed the effectiveness of the proposed method.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Fault dictionary based approach is known to be a popular diagnosis method. In this approach, output responses are compared between a circuit under diagnosis and an associated fault dictionary to deduce candidate faults. A fault dictionary that contains output values at all the primary outputs for all the test patters and for all the target faults is called full response dictionary, and its size tends to be very large. Therefore, for practical reasons the fault dictionary size needs to be reduced. In this paper we propose a test pattern ordering method for reducing the fault dictionary size. For example, let's consider a case where a certain fault f exists in a circuit under diagnosis. If first n test patterns are sufficient to deduce fault f as the only candidate fault, then the dictionary does not need to store the output responses for fault f with the test patterns other than the first n test patterns. The proposed method applies a heuristic approach to determine the order of test patterns to reduce the size of fault dictionary to be stored. Experimental results show the effectiveness of the proposed method.

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Field testing and field diagnosis are effective ways for achieving high reliability of modern systems. Since they are executed during an idle mode or a start-up mode in a system, they must be completed within very short time. Adaptive diagnosis applies test patterns selectively according to a candidate faults set that is obtained during the fault diagnosis process. In this paper, we propose an adaptive fault diagnosis method using a compact dictionary in order to reduce compute time for deducing candidate faults. A compact dictionary is created by compacting some output values into one bit. Although the compute time is reduced using a compact dictionary, the number of applied test patterns for diagnosis may increase in some cases. We investigate the relation between the size of a compact dictionary, compute time and the number of test patterns by experiments for benchmark circuits.

DOI： 10.1109/ITC-CSCC.2019.8793429

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When a system is in idle/starting-up state, Field-Testing is a promising way to guarantee the reliability of an advanced system. However, the extremely limited test application time obstructs the implementation of field test. In this paper, we introduce a test pattern partitioning approach by using two well-known machine learning algorithms: Simulated Annealing (SA) and Support Vector Machines (SVM), to derive an optimal solution for pattern partitioning that minimizes the test latency for high reliability. From the experimental results on benchmark circuit we show that both SA and SVM based method can significantly improve the test latency of partition test, and SVM is much more efficient than SA. Those results confirm the feasibility of machine learning algorithm for the pattern partition problem.

DOI： 10.1109/ITC-CSCC.2019.8793328

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Multi-cycle test with partial observation for scan-based logic BIST is known as one of effective methods to improve fault coverage without increase of test time. In the method, the selection of flip-flops for partial observation is critical to achieve high fault coverage with small area overhead. This paper proposes a selection method under the limitation to a number of flip-flops. The method consists of structural analysis of CUT and logic simulation of test vectors, therefore, it provides an easy implementation and a good scalability. Experimental results on benchmark circuits show that the method obtains higher fault coverage with less area overhead than the original method. Also the relation between the number of selected flip-flops and fault coverage is investigated.

DOI： 10.1109/ATS.2018.00017

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Other Link： https://dblp.uni-trier.de/db/conf/ats/ats2018.html#OshimaKWSK18

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE Computer Society  

DOI： 10.1109/MDAT.2018.2799801

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

Recently, reconfigurable devices are gaining increased attention for the development of IoT, Automotive and AI system. A new type of fine-grained reconfigurable device named MRLD (Memory Based Reconfigurable Logic Device) has been proposed which is constructed by general SRAMs without any programmable interconnect resources. It should be a promising alternative to FPGA with the benefits of low production cost, low power and small delay. In this paper, we overview the architecture and the operation principle of MRLD. We also propose a test strategy and algorithms of pattern generation for the interconnect defects referred to stuck-at and bridge faults under MRLD. Experimental results confirmed the effectiveness of the proposed test method.

DOI： 10.1109/ATS.2017.16

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Other Link： https://dblp.uni-trier.de/db/conf/ats/ats2017.html#WangHTSKS17

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

Multi-cycle Test applies more than one capture cycles during the capture operation which is a promising way to reduce the test volume of Logic-BIST (Logic Built-in Self-Test) based POST (Power-on Self-Test) for achieving high fault coverage. However, the randomness loss of the capture patterns due to the large number of capture cycles obstructs the further improvement of fault coverage and pattern reduction. In this paper, we propose a novel approach to control the capture patterns by modifying the captured values of scan Flip-Flops (FFs) during capture operation to enhance the test quality of the capture patterns. In the approach, we insert FF-Control circuits between the scan FFs and the combinational circuit to improve the randomness of the capture patterns by loading toggle vectors/pseudo-random vectors. The experimental results of ISCAS89 and ITC99 benchmarks validated the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction for Logic-BIST.

DOI： 10.1109/ATS.2018.00038

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To attain the requirement of ISO26262 standard, the POST for automotive MCU needs to achieve high Latent Fault (LF) metric (>90% for ASIL D) within limited test application time (TAT). In this paper, we propose a new DFT technique named Fault-Detection-Strengthened (FDS) method to enhance the effect of test pattern reduction of the multi-cycle test for shortening the TAT of POST, and develop an original in-house tool named FVP-TPI (Fault Vanishing Point-TPI) to implement the FDS method to automotive MCU. The evaluation results on a latest commercial automotive MCU (62M gates) confirm the effectiveness (test volume compaction) and the practicability (smaller hardware overhead, shorter period of DFT) of the method.

DOI： 10.1109/ETS.2018.8400707

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC  

High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips.

DOI： 10.1109/TETC.2017.2767070

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：Institute of Electronics, Information and Communication, Engineers, IEICE  

In this paper, we propose a method to diagnose a bridging fault between a clock line and a gate signal line. Assuming that scan based flush tests are applied, we perform fault simulation to deduce candidate faults. By analyzing fault behavior, it is revealed that faulty clock waveforms depend on the timing of the signal transition on a gate signal line which is bridged. In the fault simulation, a backward sensitized path tracing approach is introduced to calculate the timing of signal transitions. Experimental results show that the proposed method deduces candidate faults more accurately than our previous method.

DOI： 10.1587/transinf.2016EDL8210

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.

DOI： 10.1109/ATS.2016.59

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Other Link： https://dblp.uni-trier.de/db/conf/ats/ats2016.html#KatoWSKW16

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE  

BIST based field testing is a promising way to guarantee the functional safety of intelligent and autonomous systems. To improve the fault coverage with less random patterns for BIST, sequentially observing some flip-flops(FFs) during multi-cycle test is useful. In this paper, we propose the methodology for selecting the Fault-Detection-Strengthened FFs in multi-cycle test by evaluating the structure of a circuit. The experimental results of ITC99 benchmarks and a real Electronic Control Unit (ECU) circuit show the effectiveness of the proposed methods in fault coverage improvement and random pattern reduction.

DOI： 10.1109/ATS.2016.40

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Other Link： https://dblp.uni-trier.de/db/conf/ats/ats2016.html#WangAHHTIM16

Language：English   Publishing type：Research paper (scientific journal)   Publisher：Information Processing Society of Japan  

For the purpose of analyzing the cause of delay in modern digital circuits, efficient diagnosis methods for delay faults need to be developed. This paper presents diagnosis methods for gate delay faults by using a fault dictionary approach. Although a fault dictionary is created by fault simulation and for a specific amount of delay, the proposed method using it can deduce candidate faults successfully even when the amount of delay in a circuit under diagnosis is different from that of the delay assumed during the fault simulation. In this paper, we target diagnosing the presence of single gate delay faults and double gate delay faults. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed methods.

DOI： 10.2197/ipsjtsldm.9.13

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Language：English   Publishing type：Research paper (scientific journal)   Publisher：American Scientific Publishers  

High power dissipation in scan-based Logic-BIST testing is a vital issue. Low power approaches to handle all power problems of Logic-BIST have been proposed in our prior works, in which the toggle rate (switching activity) during the test operation (scan and capture) is well controlled. While significant reduction of the toggle rate has been confirmed, the amount of power reduction on a real chip is not known yet. In this paper, we implement the low power approaches on a Test Element Group (TEG) chip to investigate the physical effects of the low power scheme on a real chip in terms of current dissipation, voltage-drop and delay variations. Experimental results confirm the effectiveness of the low power scheme and show strong correlation between the simulated toggle rate and the measured (current, voltage-drop and delay variation) values. They show that the simulated toggle rate can be used as a good indicator of test power in test generation or design. The measured results of the actual power reduction caused by the toggle rate reduction should be valuable references to the low power test design.

DOI： 10.1166/jolpe.2015.1410

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Language：English   Publishing type：Part of collection (book)   Publisher：Springer International Publishing  

Since the 3D integrated circuit (3D-IC) consists of several dies that are connected by the huge number of through-silicon vias (TSVs), the yield of a 3D-IC makes an impact on the chip cost. Therefore, development of testing technology for 3D-IC becomes essential for reducing the manufacturing cost of 3D-IC. In this chapter, we describe the testing technologies for 3D-IC. In Sect. 8.1, we marshal the issues that must be handled in the 3D-IC testing. From Sects. 8.2 to 8.4, we introduce the outlining of the proposed 3D-IC testing technologies in so far. From Sects. 8.5 to 8.7, we provide the 3D-IC testing technologies that are proposed by our research group in Japan.

DOI： 10.1007/978-3-319-18675-7_8

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It is very difficult, if not impossible, to design hazard free circuits in view of substantial delay uncertainties of gates and interconnects implemented in submicron technologies. In this paper, we propose diagnosis methods for gate delay faults for such circuits. The fault simulation method employed by us uses eight values and calculates logic values as well as earliest transition times and latest transition times. It can deal with hazard signals more accurately than conventional methods. The proposed method uses a fault dictionary to deduce candidate faults which sufficiently explain the output responses of a circuit under diagnosis.

DOI： 10.1109/ISVLSI.2015.67

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2015.67

Language：English   Publishing type：Doctoral thesis  

Advances in semiconductor process technology have resulted in various aging issues in field operation of Very Large Scale Integration (VLSI) circuits. For example, HCI (Hot carrier injection), BTI (Bias Temperature Instability), TDDB (Time Dependent Dielectric Breakdown) are well-known aging phenomena, and they can increase the circuit delay resulting in serious reliability problems. In order to avoid system failures caused by aging, recent design usually sets a certain timing margin in operational frequency of the circuit. However, it is difficult to determine the size of the proper timing margin because of the difficulty of prediction of its aging speed in actual use that is related to operational environment. Pessimistic prediction may result in performance sacrificing although it will improve the reliability of the system. BIST-based field test is a promising way to guarantee the reliability of the circuit through detecting the aging-induced faults during the circuit operation. However, the field test has a limitation on test application time, which makes it difficult to achieve high test quality. Therefore an effective test application method at field is required. In addition to the requirement of short test application time, the BIST-based field test requires performing at-speed testing in order to detect timing-related defects. However, it is well known that power dissipation during testing is much higher than that in normal circuit operation. Because excessive power dissipation causes higher IR-drop and higher temperature, it results in delay increase during testing, and in turn, causing false at-speed testing and yield loss. While many low power test methods have been proposed to tackle the test power issue, inadequate test power reduction and lower fault coverage still remain as important issues. Moreover, low power testing that just focuses on power reduction is insufficient. When the test power is reduced to a very low level, a timing-related defect may be missed by the test, and a defective circuit will appear to be a good part passing the test. Therefore, appropriate test power control is necessary though it was out of considering in the existing methods. In this dissertation, we first proposed a new test application to satisfy the limitation of short test application time for BIST-based field test, and then we proposed a new low power BIST scheme that focuses on controlling the test power to a specified value for improving the field test quality. In chapter 3, a new field test application method named “rotating test” is presented in which a set of generated test patterns to detect aging-induced faults is partitioned into several subsets, and apply each subset in one test session at field. In order to maximize the test quality for rotating test, we proposed test partitioning methods that refer to two items: First one aims at maximizing fault coverage of each subset obtained by partitioning. Second one aims at minimizing the detection time interval of all faults in rotating test to avoid system failures. Experimental results demonstrated the effectiveness of the proposed partitioning methods. In chapter 4, we proposed a new low power BIST scheme which can control the scan-in power, scan-out power and capture power while keeping test coverage at high level. In this scheme, a new circuit called pseudo low-pass filter (PLPF) is developed for scan-in power control, and a multi-cycle capture test technique is employed to reduce the capture power. In order to control scan-out power dissipated by test responses, we proposed a novel method that selects some flip-flops in scan chains at logic design phase, and fills the selected flip-flops with proper values before starting scan-shift operation so as to reduce the switching activity associated with scan-out. The experimental results for ISCAS-89 and ITC-99 benchmark circuits show that significant scan-in power reduction rate (the original rate of 50% is reduced to 7~8%) and capture power reduction rate (the original rate of 20% is reduced to 6~7%) were derived. With the scan-out controlling method, the scan-out power can be reduced from 17.2% to 8.4%, which could not be achieved by the conventional methods. Moreover, in order to control the test power to the specified rate to accommodate the various test power requirements. A scan-shift power controlling scheme was also discussed. It showed the capability of controlling any scan-shift toggle rate between 6.7% and 50%.

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：Institute of Electronics, Information and Communication, Engineers, IEICE  

In this paper we propose a novel method to reduce power consumption during scan testing caused by test responses at scan-out operation for logic BIST. The proposed method overwrites some flip-flops (FFs) values before starting scan-shift so as to reduce the switching activity at scan-out operation. In order to relax the fault coverage loss caused by filling new FF values before observing the capture values at the FFs, the method employs multi-cycle scan test with partial observation. For deriving larger scan-out power reduction with less fault coverage loss and preventing hardware overhead increase, the FFs to be filled are selected in a predetermined ratio. For overwriting values, we prepare three value filling methods so as to achieve larger scan-out power reduction. Experiment for ITC99 benchmark circuits shows the effectiveness of the methods. Nearly 51% reduction of scan-out power and 57% reduction of peak scanout power are achieved with little fault coverage loss for 20% FFs selection, while hardware overhead is little that only 0.05%. Copyright © 2013 The Institute of Electronics, Information and Communication Engineers.

DOI： 10.1587/transinf.E96.D.2012

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Other Link： http://dblp.uni-trier.de/db/journals/ieicet/ieicet96d.html#journals/ieicet/WangSKM13

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

High test power in logic BIST is a serious problem not only for production test, but also for board test, system debug or field test. Many low power BIST approaches that focus on scan-shift power or capture power have been proposed. However, it is known that a half of scan-shift power is compensated by test responses, which is difficult to control in those approaches. This paper proposes a novel approach that directly reduces scan-out power by modifying some flip-flops' values in scan chains at the last capture. Experimental results show that the proposed method reduces scan-out power up to 30% with little loss of test coverage. © 2012 IEEE.

DOI： 10.1109/ATS.2012.50

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Other Link： http://doi.ieeecomputersociety.org/10.1109/ATS.2012.50

Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophisticated methods are proposed for scan-test, there are not so many for logic BIST because of its uncontrollable randomness. However, logic BIST currently becomes vital for system debug or field test. This paper proposes a novel low power BIST technology that reduces shift-power by eliminating the specified high-frequency parts of vectors and also reduces capture power. The authors show that the proposed technology not only reduces test power but also keeps test coverage with little loss. © 2012 IEEE.

DOI： 10.1109/ATS.2012.27

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Language：English   Publishing type：Research paper (international conference proceedings)   Publisher：IEEE Computer Society  

Segmented testing, in which a set of test patterns are partitioned into several segments, has been shown to be applicable for on-line testing as it can shorten the mean time to fault detection. One problem that exists for segmented testing is how to partition the set of tests so that the detection latency can be minimized. In this paper, we first propose a method to compute a lower bound of detection latency. Then we present a genetic algorithm (GA) based procedure to partition a given test set into several test segments aiming to reduce the detection latency. Experimental results on ISCAS'89 benchmark circuits demonstrate that the proposed approach can effectively reduce detection latency. © 2011 IEEE.

DOI： 10.1109/DSNW.2011.5958841

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DOI： 10.11486/ejisso.34.0_4c1-02

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Resistive Open Faults (RoF) are known to be major sources of small delays in Deep Sub-Micron devices. Excessive IR drop during test results in delay variation that would cause incorrect diagnosis for small delay faults such as RoFs. We believe that the patterns with low IR drop can help avoid incorrect diagnosis. Therefore, we propose a test pattern selection method for RoF diagnosis under the constraint of low IR drop. Our method first selects the patterns for target faults whose longest sensitized path have high IR drop from a pre-generated test set, and then it conducts x-identification and x-filling on the risky pattern set to generate safety patterns with low IR drop for the target faults. Simulated Annealing algorithm is introduced for exploring the best x-filling. Experimental results show the effectiveness of our selection.

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Voltage drop by a momentary current change during capture cycles in scan-based testing brings an increase in path delay of a circuit under test, and is one of factors of test accuracy degradation. Multi-cycle test is a method that can reduce the voltage drop by repetition of the capture operation. This paper investigates how the reduction of switching activities by the multi-cycle test method reduces the actual voltage drop from observation of power supply voltage of a TEG chip implementing a low-power BIST.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Excessive power dissipation in logic BIST is a serious problem. Although many low power BIST approaches that focus on scan-in power or capture power have been proposed, there are not so many techniques for scan-out power reduction due to the difficulty in controlling the captured test responses. In this paper, we propose a novel scan-out power reduction method for multi-cycle BIST that directly reduces scan-out power by modifying some flip-flops' values in scan chains at the last capture, and without sacrificing the test coverage.

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Language：Japanese   Publisher：The Institute of Electronics, Information and Communication Engineers  

Low-power test technology has been investigated deeply to achieve an accurate and efficient testing. Although many sophisticated methods are proposed for scan-test, there are not so many for logic BIST because of its uncontrollable randomness. However, logic BIST currently becomes vital for system debug or field test. This paper proposes a novel low power BIST technology that eliminates the specified high-frequency parts of vectors in scan-shift and also reduces capture power. The authors show that the proposed technology not only reduces test power but also controls test power with little loss of test coverage.

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Event date： 2020.9

Language：Japanese   Presentation type：Public lecture, seminar, tutorial, course, or other speech  

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Language：Japanese   Presentation type：Oral presentation (general)  

File： 2022boundary_scan.pdf

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